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    • 34. 发明申请
    • METHOD FOR MANUFACTURING DISPLAY PANEL AND DISPLAY DEVICE SUBSTRATE
    • 制造显示面板和显示设备基板的方法
    • US20110279023A1
    • 2011-11-17
    • US13146132
    • 2010-01-19
    • Yukiya NishiokaTakashi KuriharaMasaru Kajitani
    • Yukiya NishiokaTakashi KuriharaMasaru Kajitani
    • H05B33/02H05B33/10
    • H01L27/3253H01L27/322
    • A method for manufacturing a display panel comprises the steps of: forming a display device substrate 60 by providing on a first substrate 20, which is equipped with a color filter 30 on which a plurality of filter elements are arranged, a plurality of organic electroluminescent elements 40, which have the same structure as each other and which is individually equipped with a connection electrode formed with a connection terminal 46a, so that each of organic electroluminescent elements is overlapped with each of the filter elements; preparing a driving substrate 50, which comprises a driving circuit for driving the plurality of and a connection portion 52a that establishes electrical connection to the driving circuit; arranging a laminating material 74X on a surface of the display device substrate or the driving substrate so as to enclose the plurality of organic electroluminescent elements when the display device substrate and the driving substrate are laminated; and laminating the display device substrate and the driving substrate so that the connection terminal and the connection portion come into contact each other.
    • 一种制造显示面板的方法包括以下步骤:通过在第一基板20上设置显示装置基板60,第一基板20配备有多个滤色器元件布置在其上的滤色器30,多个有机电致发光元件 40,它们具有彼此相同的结构,并且分别配备有形成有连接端子46a的连接电极,使得每个有机电致发光元件与每个过滤元件重叠; 制备驱动基板50,其包括用于驱动多个的驱动电路和与驱动电路建立电连接的连接部分52a; 在显示装置基板和驱动基板层叠时,在显示装置基板或驱动基板的表面上配置层叠材料74X,以封闭多个有机电致发光元件; 并且将所述显示装置基板和所述驱动基板层叠,使得所述连接端子和所述连接部彼此接触。
    • 38. 发明授权
    • Surge protector
    • 浪涌保护器
    • US07660095B2
    • 2010-02-09
    • US10565422
    • 2004-07-13
    • Yasuhiro ShatoTuyoshi OgiMiki AdachiSung-Gyoo LeeTakashi KuriharaToshiaki Ueda
    • Yasuhiro ShatoTuyoshi OgiMiki AdachiSung-Gyoo LeeTakashi KuriharaToshiaki Ueda
    • H02H1/00
    • H01T4/12Y10T29/49082Y10T29/49107Y10T29/49128
    • A surge protector coated with an oxide layer having an excellent chemical stability at the high temperature range and excellent adherence with respect to main discharge electrodes. The surge protector includes a column-shaped ceramic member that has a conductive film divided by a discharge gap interposed therebetween; a pair of main discharge electrode members opposite to each other on both ends of the column-shaped ceramic member to come in contact with the conductive film; and a cylindrical ceramic tube which is fitted to the pair of main discharge electrode members opposite to each other to seal both the column-shaped ceramic member and sealing gas inside thereof. Oxide films are formed on main discharge surfaces of at least the protrusive supporting portions of the pair of main discharge electrode members opposite to each other, by performing an oxidation treatment, respectively.
    • 具有在高温范围内具有优异化学稳定性的氧化物层和相对于主放电电极具有优异粘附性的电涌保护器。 浪涌保护器包括柱状陶瓷构件,其具有通过插入其间的放电间隙分隔的导电膜; 一对在柱状陶瓷构件的两端彼此相对的主放电电极构件,以与导电膜接触; 和一对圆筒状的陶瓷管,该圆筒形陶瓷管与一对相对的主放电电极部件嵌合,以密封柱状陶瓷部件和内部的密封气体。 通过分别进行氧化处理,分别在一对主放电电极部件的至少突出支撑部的主放电面上形成氧化膜。
    • 40. 发明授权
    • Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program
    • 模拟半导体集成电路电源电压分配的方法和仿真程序
    • US07367000B2
    • 2008-04-29
    • US11305184
    • 2005-12-19
    • Takashi KuriharaKenji WadaMasahiro SuzukiEiji Fujine
    • Takashi KuriharaKenji WadaMasahiro SuzukiEiji Fujine
    • G06F17/50
    • G06F17/5036
    • The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven distribution of a floor plan taken into account. In Step S1, design information (Core size CS, core ring width CW, block shape BS, macro shape MS, block current BI, macro current MI, etc.) is inputted into a simulator. In Step S2, information regarding a floor plan (Block position BP, macro position MP, power I/O position IOP) is inputted into the simulator by a designer. In Step S3, the power unit management table is initialized, and resistance modeling and current source modeling are also carried out. In Step S5 (FIG. 1), the static IR drop is calculated based on the power unit management table CT obtained in Step S4.
    • 本发明的目的是提供一种用于模拟半导体集成电路的电源电压分布的方法,通过该方法可以尝试缩短制备功率单元模型所需的时间,并且可以执行高精度的仿真 考虑到平面布置的不均匀分布。 在步骤S1中,向模拟器输入设计信息(核心尺寸CS,核心环宽度CW,块形状BS,宏形状MS,块电流BI,宏观电流MI等)。 在步骤S2中,由设计者将关于平面图(块位置BP,宏位置MP,电力I / O位置IOP)的信息输入到模拟器。 在步骤S3中,对功率单元管理表进行初始化,并进行电阻建模和电流源建模。 在步骤S5(图1)中,基于在步骤S 4中获得的功率单元管理表CT计算静态IR下降。