专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08304836B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质堆叠的结构和方法
公开(公告)号：US08304836B2
公开(公告)日：2012-11-06
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

32. 发明申请

US20110115027A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 有权
标题翻译：结构和方法来获取电子尺寸的电介质堆叠
公开(公告)号：US20110115027A1
公开(公告)日：2011-05-19
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/263
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

33. 发明申请

US20100320547A1 SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC 有权
标题翻译：用于高K栅介质的SCAVANGING金属叠层
公开(公告)号：US20100320547A1
公开(公告)日：2010-12-23
申请号：US12487248
申请日：2009-06-18
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L29/78 , H01L21/314 , H01L21/336
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译：高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。

34. 发明授权

US08853751B2 Reducing the inversion oxide thickness of a high-K stack fabricated on high mobility semiconductor material 有权
标题翻译：降低在高迁移率半导体材料上制造的高K叠层的反型氧化物厚度
公开(公告)号：US08853751B2
公开(公告)日：2014-10-07
申请号：US13614962
申请日：2012-09-13
申请人： Takashi Ando , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L29/772 , H01L29/78 , H01L21/8234
CPC分类号： H01L21/823462 , H01L21/28255 , H01L21/28264 , H01L21/82345 , H01L29/1054 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/665 , H01L29/66522
摘要： A semiconductor structure includes a high mobility semiconductor, an interfacial oxide layer, a high dielectric constant (high-k) layer, a stack, a gate electrode, and a gate dielectric. The stack comprises a lower metal layer, a scavenging metal layer comprising a scavenging metal, and an upper metal layer formed on the scavenging metal layer. A Gibbs free energy change of a chemical reaction, in which an atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer combines with a metal oxide material comprising the scavenging metal and oxygen to form the scavenging metal in elemental form and oxide of the atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer, is positive.
摘要翻译：半导体结构包括高迁移率半导体，界面氧化物层，高介电常数（高k）层，堆叠，栅极电极和栅极电介质。堆叠包括下金属层，包含清除金属的清除金属层和形成在扫气金属层上的上金属层。化学反应的吉布斯自由能变化，其中构成直接与界面氧化物层接触的高迁移率半导体层的原子与包含清除金属和氧的金属氧化物材料结合，以形成元素形式的清除金属和氧化物构成与界面氧化物层直接接触的高迁移率半导体层的原子为正。

35. 发明授权

US08796784B2 Devices and methods to optimize materials and properties for replacement metal gate structures 有权
标题翻译：用于优化更换金属门结构的材料和性能的设备和方法
公开(公告)号：US08796784B2
公开(公告)日：2014-08-05
申请号：US13604036
申请日：2012-09-05
申请人： Takashi Ando , Christian Lavoie , Vijay Narayanan
发明人： Takashi Ando , Christian Lavoie , Vijay Narayanan
IPC分类号： H01L21/02
CPC分类号： H01L29/66545 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/324 , H01L29/165 , H01L29/456 , H01L29/66606 , H01L29/66628 , H01L29/7848
摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.
摘要翻译：用于器件制造的器件和方法包括用牺牲材料形成栅极结构。硅化区域形成在与栅极结构相邻的源极/漏极区域上，或者形成在源极/漏极区域内的沟槽触点的底部。对源极/漏极区域或硅化物区域进行处理，以建立对后续热处理的阻力，并调整肖特基势垒高度，从而降低接触电阻。金属触点形成为与硅化物区域接触。去除牺牲材料并用替换导体代替。

36. 发明授权

US08785322B2 Devices and methods to optimize materials and properties for replacement metal gate structures 失效
公开(公告)号：US08785322B2
公开(公告)日：2014-07-22
申请号：US13017809
申请日：2011-01-31
申请人： Takashi Ando , Christian Lavoie , Vijay Narayanan
发明人： Takashi Ando , Christian Lavoie , Vijay Narayanan
IPC分类号： H01L21/4763 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/324 , H01L29/165 , H01L29/456 , H01L29/66606 , H01L29/66628 , H01L29/7848
摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

37. 发明授权

US08404530B2 Replacement metal gate with a conductive metal oxynitride layer 有权
标题翻译：替代金属栅极与导电金属氧氮化物层
公开(公告)号：US08404530B2
公开(公告)日：2013-03-26
申请号：US13177692
申请日：2011-07-07
申请人： Takashi Ando , Vijay Narayanan
发明人： Takashi Ando , Vijay Narayanan
IPC分类号： H01L21/338
CPC分类号： H01L21/28088 , H01L21/28176 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A disposable gate structure and a gate spacer are formed on a semiconductor substrate. A disposable gate material portion is removed and a high dielectric constant (high-k) gate dielectric layer and a metal nitride layer are formed in a gate cavity and over a planarization dielectric layer. The exposed surface portion of the metal nitride layer is converted into a metal oxynitride by a surface oxidation process that employs exposure to ozonated water or an oxidant-including solution. A conductive gate fill material is deposited in the gate cavity and planarized to provide a metal gate structure. Oxygen in the metal oxynitride diffuses, during a subsequent anneal process, into a high-k gate dielectric underneath to lower and stabilize the work function of the metal gate without significant change in the effective oxide thickness (EOT) of the high-k gate dielectric.
摘要翻译：在半导体衬底上形成一次性栅极结构和栅极间隔物。去除一次性栅极材料部分，并且在栅极腔中和平坦化介电层上形成高介电常数（高k）栅极电介质层和金属氮化物层。金属氮化物层的暴露表面部分通过使用暴露于臭氧化水或含氧化剂的溶液的表面氧化工艺转化为金属氮氧化物。导电栅极填充材料沉积在栅极腔中并被平坦化以提供金属栅极结构。金属氧氮化物中的氧在随后的退火过程中扩散到下面的高k栅极电介质中，以降低和稳定金属栅极的功函数，而不会在高k栅极电介质的有效氧化物厚度（EOT）上显着变化。

38. 发明申请

US20120326216A1 DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES 有权
公开(公告)号：US20120326216A1
公开(公告)日：2012-12-27
申请号：US13604036
申请日：2012-09-05
申请人： Takashi Ando , Christian Lavoie , Vijay Narayanan
发明人： Takashi Ando , Christian Lavoie , Vijay Narayanan
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/324 , H01L29/165 , H01L29/456 , H01L29/66606 , H01L29/66628 , H01L29/7848
摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

39. 发明申请

US20110115026A1 CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES 有权
标题翻译： CMOS器件的高K金属栅极堆叠和结构中阈值电压的控制
公开(公告)号：US20110115026A1
公开(公告)日：2011-05-19
申请号：US12619209
申请日：2009-11-16
申请人： Hemanth Jagannathan , Takashi Ando , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/78 , H01L21/20
CPC分类号： H01L21/823857 , H01L21/28176 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/6659 , H01L29/66651
摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.
摘要翻译：用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。栅极堆叠包括形成在半导体衬底上的锗（Ge）材料层，形成在Ge材料层上的扩散阻挡层，在扩散阻挡层上形成的具有大于约3.9的高介电常数的高k电介质，以及形成在高k电介质层上方的导电电极层。

40. 发明申请

US20100308412A1 CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES 有权
标题翻译：用于CMOS器件的高K金属栅极堆栈和结构中的平面电压和阈值电压的控制
公开(公告)号：US20100308412A1
公开(公告)日：2010-12-09
申请号：US12477536
申请日：2009-06-03
申请人： Hemanth Jagannathan , Takashi Ando , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Vijay Narayanan
IPC分类号： H01L29/78 , H01L27/092 , H01L21/28
CPC分类号： H01L21/823857 , H01L21/28167 , H01L21/28194 , H01L21/823842 , H01L27/092 , H01L29/513 , H01L29/78
摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.
摘要翻译：用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。栅极堆叠包括具有大于约3.9的高介电常数的高k电介质，与高k电介质接合的锗（Ge）材料层，以及设置在高k电介质或Ge材料上方的导电电极层层。栅极堆叠优化了平带电压或阈值电压的偏移，以在p-FET器件中获得高性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式