专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08288221B2 Method of manufacturing semiconductor device and semiconductor device 失效
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US08288221B2
公开(公告)日：2012-10-16
申请号：US12537875
申请日：2009-08-07
申请人： Takahisa Eimori , Nobuyuki Mise
发明人： Takahisa Eimori , Nobuyuki Mise
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/02164 , H01L21/02178 , H01L21/02181 , H01L21/02194 , H01L21/022 , H01L21/02321 , H01L21/31612 , H01L21/31645 , H01L21/823842 , H01L27/11 , H01L27/1104
摘要： A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO2) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and a protective film having humidity resistance and oxidation resistance is formed on the metal thin film. Then, by diffusing the entire metal element of the metal thin film into the base insulating film in a state of having the protective film, a mixed film (high dielectric constant film) thicker than the silicon oxide film and having a higher dielectric constant than silicon oxide and containing hafnium and oxygen of the base insulating film and the metal element of the metal thin film is formed on the silicon oxide film.
摘要翻译：在形成在基板的主表面上的氧化硅（SiO 2）膜上形成含有铪和氧的基极绝缘膜。随后，在基底绝缘膜上形成比基底绝缘膜薄且仅由金属元件制成的金属薄膜，并且在金属薄膜上形成具有耐湿性和抗氧化性的保护膜。然后，通过在具有保护膜的状态下将金属薄膜的整个金属元素扩散到基底绝缘膜中，比硅氧化膜厚且具有比硅更高的介电常数的混合膜（高介电常数膜）在氧化硅膜上形成氧化物并含有基底绝缘膜的铪和氧和金属薄膜的金属元素。

32. 发明申请

US20080308869A1 SEMICONDUCTOR DEVICE WHICH HAS MOS STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有MOS结构的半导体器件及其制造方法
公开(公告)号：US20080308869A1
公开(公告)日：2008-12-18
申请号：US12194631
申请日：2008-08-20
申请人： Hidekazu ODA , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
发明人： Hidekazu ODA , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.
摘要翻译：可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱有了这个。当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

33. 发明申请

US20070007602A1 Semiconductor device which has MOS structure and method of manufacturing the same 审中-公开
标题翻译：具有MOS结构的半导体器件及其制造方法
公开(公告)号：US20070007602A1
公开(公告)日：2007-01-11
申请号：US11478669
申请日：2006-07-03
申请人： Hidekazu Oda , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
发明人： Hidekazu Oda , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
IPC分类号： H01L29/94
CPC分类号： H01L21/823842
摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.
摘要翻译：可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱有了这个。当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

34. 发明授权

US06573171B2 Semiconductor device and manufacturing process thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06573171B2
公开(公告)日：2003-06-03
申请号：US09760641
申请日：2001-01-17
申请人： Takahisa Eimori , Hiroshi Kimura
发明人： Takahisa Eimori , Hiroshi Kimura
IPC分类号： H01L213205
CPC分类号： H01L27/10844 , H01L21/76897
摘要： In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.
摘要翻译：在需要在存储单元阵列区域的外围的层之间的导电路径的外围电路区域中，在从导体的接触部分的区域去除用于自对准接触的氮化硅膜之后，提供导电路径，通过在导体上形成层间氧化膜，并提供通过层间氧化膜的开口。或者，通过在整个层间氧化膜和氮化硅膜上形成开口，在用于自对准接触的氮化硅膜上形成层间氧化膜之后，提供导电路径。

35. 发明授权

US06268278B1 Semiconductor device and manufacturing process thereof 失效
公开(公告)号：US06268278B1
公开(公告)日：2001-07-31
申请号：US09283752
申请日：1999-04-02
申请人： Takahisa Eimori , Hiroshi Kimura
发明人： Takahisa Eimori , Hiroshi Kimura
IPC分类号： H01L214763
CPC分类号： H01L27/10844 , H01L21/76897
摘要： In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.

36. 发明授权

US6087710A Semiconductor device having self-aligned contacts 失效
标题翻译：具有自对准触点的半导体器件
公开(公告)号：US6087710A
公开(公告)日：2000-07-11
申请号：US687624
申请日：1996-07-26
申请人： Takahisa Eimori , Hiroshi Kimura
发明人： Takahisa Eimori , Hiroshi Kimura
IPC分类号： H01L23/522 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L23/48
CPC分类号： H01L27/10844 , H01L21/76897
摘要： In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.
摘要翻译：在需要在存储单元阵列区域的外围的层之间的导电路径的外围电路区域中，在从导体的接触部分的区域去除用于自对准接触的氮化硅膜之后，提供导电路径，通过在导体上形成层间氧化膜，并提供通过层间氧化膜的开口。或者，通过在整个层间氧化膜和氮化硅膜上形成开口，在用于自对准接触的氮化硅膜上形成层间氧化膜之后，提供导电路径。

37. 发明授权

US5834817A Field effect transistor with a shaped gate electrode 失效
公开(公告)号：US5834817A
公开(公告)日：1998-11-10
申请号：US983931
申请日：1992-12-01
申请人： Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori
发明人： Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/43 , H01L29/78
CPC分类号： H01L29/66598 , H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/6659
摘要： A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

38. 发明授权

US5459344A Stacked capacitor type semiconductor memory device and manufacturing method thereof 失效
标题翻译：叠层电容器型半导体存储器件及其制造方法
公开(公告)号：US5459344A
公开(公告)日：1995-10-17
申请号：US727783
申请日：1991-07-10
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

39. 发明授权

US5442212A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5442212A
公开(公告)日：1995-08-15
申请号：US292303
申请日：1994-08-18
申请人： Takahisa Eimori
发明人： Takahisa Eimori
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68
CPC分类号： H01L27/10808
摘要： In a semiconductor memory device, pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized.
摘要翻译：在半导体存储器件中，位线的间距大于字线的间距，并且存储节点接点位于由位线和字线包围的每个矩形区域中。相邻存储节点触点的中心之间的距离以及位线接触的中心与相邻的存储节点触点之间的距离都大于字线的间距。通过这种结构，可以增加每单位存储单元的平面面积，可以扩大存储节点与存储节点接触点之间的配准余量，从而防止位线与存储节点接触之间的短路，从而存储单元结构可以实现高产量和高可靠性。

40. 发明授权

US5278437A Stacked capacitor type semiconductor memory device and manufacturing method thereof 失效
标题翻译：叠层电容器型半导体存储器件及其制造方法
公开(公告)号：US5278437A
公开(公告)日：1994-01-11
申请号：US947615
申请日：1992-09-21
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式