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31. 发明申请

US20060024874A1 Methods of forming a multi-bridge-channel MOSFET 有权
标题翻译：形成多桥MOSFET的方法
公开(公告)号：US20060024874A1
公开(公告)日：2006-02-02
申请号：US11190695
申请日：2005-07-26
申请人： Eun-jung Yun , Sung-min Kim , Sung-young Lee
发明人： Eun-jung Yun , Sung-min Kim , Sung-young Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66772
摘要： A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections. The through tunnels are surrounded by the first source and drain regions and the channel patterns. A gate is formed along with a gate dielectric layer, the gate filling the through tunnels and extending onto the first stacked portion.
摘要翻译：可以通过在包括沟道层和介于沟道层之间的沟道间层的衬底上形成层叠结构来形成多桥沟MOSFET（MBCFET）。通过选择性地蚀刻堆叠结构形成沟槽。沟槽横跨层叠结构彼此平行地延伸，并且将包括通道图案和沟道间图案的第一堆叠部分与第二堆叠部分分开，包括残留在第一堆叠部分两侧的通道和通道间层。使用选择性外延生长生长第一源区和漏区。第一源极和漏极区域填充沟槽并连接到由第二堆叠部分限定的第二源极和漏极区域。选择性地暴露第一堆叠部分的通道间图案的边缘部分。通过从暴露的边缘部分开始选择性地去除第一堆叠部分的通道间图案，形成通道。穿通隧道被第一源极和漏极区域以及沟道图案包围。栅极与栅极电介质层一起形成，栅极填充通孔并延伸到第一堆叠部分上。

32. 发明申请

US20050003628A1 Methods of etching intermediate silicon germanium layers using ion implantation to promote selectivity 有权
标题翻译：使用离子注入蚀刻中间硅锗层以提高选择性的方法
公开(公告)号：US20050003628A1
公开(公告)日：2005-01-06
申请号：US10884749
申请日：2004-07-02
申请人： Eun-jung Yun , Sung-young Lee , Chang-sub Lee , Sung-min Kim , Dong-gun Park
发明人： Eun-jung Yun , Sung-young Lee , Chang-sub Lee , Sung-min Kim , Dong-gun Park
IPC分类号： H01L21/20 , H01L21/265 , H01L21/306 , H01L21/76
CPC分类号： H01L21/30604
摘要： An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.
摘要翻译：通过在包括上下Si层和中间SiGex层的结构上形成具有窗口的注入掩模，可以形成集成电路器件结构。离子通过上部Si层进入植入掩模中通过窗口暴露的中间SiGex层的一部分，并将离子注入到窗口外部的中间SiGex层的部分中。蚀刻窗口外部的中间SiGex层的部分，并且通过其中注入离子的窗口露出的中间SiGex层的部分基本上不被蚀刻以形成图案化的中间SiGex层。

33. 发明申请

US20060240622A1 Multi-channel semiconductor device and method of manufacturing the same 审中-公开
标题翻译：多通道半导体器件及其制造方法
公开(公告)号：US20060240622A1
公开(公告)日：2006-10-26
申请号：US11407607
申请日：2006-04-20
申请人： Sung-young Lee , Eun-jung Yun
发明人： Sung-young Lee , Eun-jung Yun
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66795 , H01L29/78645
摘要： Provided are a multi-channel semiconductor device and a method for manufacturing the semiconductor device through a simplified process. A sacrificial layer and a channel layer are alternately stacked on a semiconductor substrate. Thereafter, the sacrificial layer and the channel layer are etched to form a separated active pattern, and a device isolation layer is formed to cover sidewalls of the active pattern. Dopant ions are implanted into the entire semiconductor substrate, thereby forming a channel separation region under the active pattern. A portion of the active pattern is etched to separate the active pattern from a pair of facing sidewalls of the device separation layer, thereby forming a channel pattern having a pair of first exposed sidewalls. Source/drain semiconductor layers are formed on the first sidewalls of the channel pattern, and a part of the device isolation layer is removed to expose a pair of second sidewalls of the channel pattern contacting with the device separation layer. Thereafter, the sacrificial layer included in the channel pattern is remove, and a conductive layer for a gate electrode is formed to cover the channel layer exposed by the removing of the sacrificial layer.
摘要翻译：提供了一种多通道半导体器件和通过简化工艺制造半导体器件的方法。牺牲层和沟道层交替堆叠在半导体衬底上。此后，蚀刻牺牲层和沟道层以形成分离的有源图案，并且形成器件隔离层以覆盖活性图案的侧壁。将掺杂离子注入到整个半导体衬底中，从而在活性图案下形成沟道分离区。蚀刻有源图案的一部分以将活性图案与器件分离层的一对相对的侧壁分离，从而形成具有一对第一暴露侧壁的沟道图案。源极/漏极半导体层形成在沟道图案的第一侧壁上，并且去除器件隔离层的一部分以暴露与器件分离层接触的沟道图案的一对第二侧壁。此后，去除包括在沟道图案中的牺牲层，并且形成用于栅电极的导电层以覆盖通过去除牺牲层而暴露的沟道层。

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