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31. 发明授权

US08709895B2 Manufacturing method power semiconductor device 有权
标题翻译：制造方法功率半导体器件
公开(公告)号：US08709895B2
公开(公告)日：2014-04-29
申请号：US13038346
申请日：2011-03-01
申请人： Sung-Shan Tai , Hung-Sheng Tsai
发明人： Sung-Shan Tai , Hung-Sheng Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.
摘要翻译：本发明提供一种功率半导体器件的端接结构及其制造方法。功率半导体器件具有有源区和端接区。终端区域围绕有源区域，终端结构设置在终端区域中。端接结构包括半导体衬底，绝缘层和金属层。半导体衬底具有设置在终端区域中的沟槽。绝缘层部分地填充到沟槽中并且覆盖半导体衬底，并且绝缘层的顶表面具有孔。金属层设置在绝缘层上，并被填充到孔中。

32. 发明申请

US20130049104A1 Method of forming a self-aligned contact opening in MOSFET 有权
标题翻译：在MOSFET中形成自对准接触开口的方法
公开(公告)号：US20130049104A1
公开(公告)日：2013-02-28
申请号：US13218476
申请日：2011-08-26
申请人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
发明人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/3105
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/41775 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
摘要翻译：提出了在半导体衬底中形成接触开口的方法。在半导体衬底中形成各自具有突出部分的多个沟槽栅极，并且在突出部分上延伸的半导体衬底上沉积停止层，其中沿着突出部分的每个侧壁的阻挡层的每个部分是被间隔物覆盖。通过利用阻挡层对间隔物的相对较高的蚀刻选择性去除未被间隔物覆盖的停止层的部分，可以形成每个侧壁上具有L型形状的相邻突出部分之间的开口，并且可以形成光刻此后可以进行处理以形成自对准的接触开口。

33. 发明授权

US08048775B2 Process of forming ultra thin wafers having an edge support ring 有权
公开(公告)号：US08048775B2
公开(公告)日：2011-11-01
申请号：US11880455
申请日：2007-07-20
申请人： Tao Feng , Sung-Shan Tai
发明人： Tao Feng , Sung-Shan Tai
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/02035 , H01L21/02013 , H01L21/3043 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

34. 发明申请

US20110223742A1 Process of forming ultra thin wafers having an edge support ring 有权
标题翻译：形成具有边缘支撑环的超薄晶片的工艺
公开(公告)号：US20110223742A1
公开(公告)日：2011-09-15
申请号：US13115097
申请日：2011-05-24
申请人： Tao Feng , Sung-Shan Tai
发明人： Tao Feng , Sung-Shan Tai
IPC分类号： H01L21/304
CPC分类号： H01L21/02035 , H01L21/02013 , H01L21/3043 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.
摘要翻译：公开了一种形成具有边缘支撑环的超薄晶片的工艺。该工艺提供了具有与旋转蚀刻工艺兼容的成角度的内壁的边缘支撑环。

35. 发明申请

US20110042724A1 Trenched mosfets with part of the device formed on a (110) crystal plane 审中-公开
标题翻译：在110平面上形成有部分器件的沟槽式mosfet
公开(公告)号：US20110042724A1
公开(公告)日：2011-02-24
申请号：US11634031
申请日：2009-04-20
申请人： Anup Bhalla , Sik K. Lui , Sung-Shan Tai
发明人： Anup Bhalla , Sik K. Lui , Sung-Shan Tai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L24/33 , H01L29/045 , H01L29/4236 , H01L29/66734 , H01L29/7811 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming the sidewalls of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.
摘要翻译：本发明公开了通过在半导体衬底的（110）晶体取向上形成沟槽的侧壁而制造的具有沟槽栅极的改进的MOSFET器件。沟槽沿着沿着半导体衬底的不同晶体取向形成的沟槽的侧壁和底表面或沟槽的终端覆盖电介质氧化物层。实施诸如氧化物退火工艺，特殊掩模或SOG工艺的特殊制造工艺以克服非均匀介电层生长的限制。

36. 发明授权

US08334566B2 Semiconductor power device having shielding electrode for improving breakdown voltage 有权
标题翻译：具有用于改善击穿电压的屏蔽电极的半导体功率器件
公开(公告)号：US08334566B2
公开(公告)日：2012-12-18
申请号：US12829349
申请日：2010-07-01
申请人： Sung-Shan Tai
发明人： Sung-Shan Tai
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0865 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： The present invention provides a semiconductor power device including a substrate, an epitaxial layer disposed on the substrate and having at least a first trench and a second trench, a gate structure disposed in the first trench, and a termination structure disposed in the second trench. The gate structure includes a gate electrode, a gate dielectric layer disposed on an upper sidewall of the first trench and between the gate electrode and the epitaxial laver, and a shield electrode disposed under the gate electrode. The termination structure includes a termination electrode and a dielectric layer disposed between the termination electrode and a sidewall of the second trench. The termination electrode and the shield electrode are connected to each other. In addition, a body region is disposed in the epitaxial layer, and the second trench is only surrounded by the body region.
摘要翻译：本发明提供了一种半导体功率器件，其包括衬底，设置在衬底上的外延层，并且具有至少第一沟槽和第二沟槽，设置在第一沟槽中的栅极结构以及设置在第二沟槽中的端接结构。栅极结构包括栅电极，设置在第一沟槽的上侧壁上以及栅电极和外延栅之间的栅电介质层，以及设置在栅极下方的屏蔽电极。端接结构包括终端电极和布置在端接电极和第二沟槽的侧壁之间的电介质层。终端电极和屏蔽电极彼此连接。此外，体区域设置在外延层中，并且第二沟槽仅被身体区域包围。

37. 发明申请

US20120083084A1 Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source 审中-公开
标题翻译：具有肖特基势垒源的非对称DMOSFET的制造方法和器件配置
公开(公告)号：US20120083084A1
公开(公告)日：2012-04-05
申请号：US13199795
申请日：2011-09-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/28518 , H01L21/823418 , H01L29/41766 , H01L29/456 , H01L29/665 , H01L29/66507 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7839 , H01L29/7845 , H01L2924/0002 , H01L2924/00 , H01L2924/1082
摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
摘要翻译：沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。围绕沟槽栅极的源极区域包括低势垒高度的金属，用作肖特基源，并且可以包括PtSi，ErSi层，并且可以是具有低势垒高度的金属硅化物层。顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。

38. 发明申请

US20120028427A1 Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET 有权
标题翻译：分闸具有不同的栅极材料和工作功能，可降低超高密度MOSFET的栅极电阻
公开(公告)号：US20120028427A1
公开(公告)日：2012-02-02
申请号：US13200882
申请日：2011-10-04
申请人： Sung-Shan Tai , YongZhong Hu
发明人： Sung-Shan Tai , YongZhong Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4958 , H01L29/66727 , H01L29/66734
摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
摘要翻译：本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

39. 发明授权

US08105905B2 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US08105905B2
公开(公告)日：2012-01-31
申请号：US12927177
申请日：2010-11-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.
摘要翻译：一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源区域短接。

40. 发明申请

US20110124167A1 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US20110124167A1
公开(公告)日：2011-05-26
申请号：US12927177
申请日：2010-11-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.
摘要翻译：一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源极区域短接触。

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