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31. 发明申请

US20130307074A1 Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate 有权
标题翻译：外延半导体电阻与半导体结构在同一基片上
公开(公告)号：US20130307074A1
公开(公告)日：2013-11-21
申请号：US13472747
申请日：2012-05-16
申请人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/13 , H01L28/20 , H01L29/0649 , H01L29/36 , H01L29/41783
摘要： An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.
摘要翻译：提供了一种电气装置，其包括具有上半导体层，埋入介质层和基底半导体层的衬底。衬底中存在至少一个限定半导体器件区域和电阻器器件区域的隔离区域。半导体器件区域包括具有存在于基极半导体层中的背栅极结构的半导体器件。与背栅结构的电接触由穿过掩埋介电层的掺杂的外延半导体柱提供。外延半导体电阻存在于电阻器件区域中。从外延半导体电阻器延伸到基底半导体层的未掺杂的外延半导体柱提供了由外延半导体电阻器产生的用于散发到基极半导体层的热通路。未掺杂和掺杂的外延半导体柱由相同的外延半导体材料组成。

32. 发明申请

US20130285152A1 FINFET WITH ENHANCED EMBEDDED STRESSOR 有权
标题翻译： FINFET与增强嵌入式压力机
公开(公告)号：US20130285152A1
公开(公告)日：2013-10-31
申请号：US13457529
申请日：2012-04-27
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/36 , H01L29/7848 , H01L29/7851
摘要： A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.
摘要翻译：鳍状物FET的沟道区域具有在平行于基底表面的第一方向上具有顶点的翅片，每个翅片从顶点向下延伸，盖子覆盖顶点和相邻鳍片之间。半导体应力区域至少沿着第一方向延伸离开翅片，以对通道区域施加应力。鳍状物FET的源极和漏极区域可以通过沟道区域彼此分离，源极和/或漏极至少部分地在半导体应力区域中。应力区域包括覆盖并从第一半导体区域延伸的第一半导体区域和第二半导体区域。第二半导体区域可以比第一半导体区域更重掺杂，并且第一和第二半导体区域可以具有相反的导电类型，其中第二半导体区域的至少一部分与第一半导体区域相交。

33. 发明申请

US20130270561A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING 审中-公开
公开(公告)号：US20130270561A1
公开(公告)日：2013-10-17
申请号：US13603661
申请日：2012-09-05
申请人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Yu Zhu , Thomas N. Adam
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Yu Zhu , Thomas N. Adam
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor device that includes providing a gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, and forming an amorphous semiconductor layer on at least a source region portion and a drain region portion of the SOI layer. The amorphous semiconductor layer is converted to a crystalline semiconductor material, wherein the crystalline semiconductor material provides a raised source region and a raised drain region of the semiconductor device. The method may be applicable to planar semiconductor devices and finFET semiconductor devices.

34. 发明申请

US20130207226A1 RECESSED DEVICE REGION IN EPITAXIAL INSULATING LAYER 审中-公开
标题翻译：外延绝缘层中的被破坏的器件区域
公开(公告)号：US20130207226A1
公开(公告)日：2013-08-15
申请号：US13371665
申请日：2012-02-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/762 , H01L29/1079 , H01L29/772 , H01L29/78603
摘要： A method for isolating semiconductor devices is described wherein an epitaxial insulating layer is grown on a semiconductor substrate. The epitaxial insulating layer is etched to form a recessed region within the layer. An epitaxial semiconductor material is grown with the recessed region to form a semiconductor device region separated from other potential device regions by non-recessed portions of the epitaxial insulating layer.
摘要翻译：其中描述了半导体器件的隔离方法，其中在半导体衬底上生长外延绝缘层。外延绝缘层被蚀刻以在层内形成凹陷区域。外延半导体材料与凹陷区域一起生长以形成通过外延绝缘层的非凹陷部分与其它电位器件区域分离的半导体器件区域。

35. 发明申请

US20130200433A1 STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES 有权
公开(公告)号：US20130200433A1
公开(公告)日：2013-08-08
申请号：US13613747
申请日：2012-09-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/02529 , H01L21/02532 , H01L21/306 , H01L21/31144 , H01L21/324 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/66795 , H01L29/66803 , H01L29/6681 , H01L29/785 , H01L29/78687
摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

36. 发明申请

US20130146953A1 Method and Structure For Forming ETSOI Capacitors, Diodes, Resistors and Back Gate Contacts 有权
标题翻译：用于形成ETSOI电容器，二极管，电阻器和后门触点的方法和结构
公开(公告)号：US20130146953A1
公开(公告)日：2013-06-13
申请号：US13316641
申请日：2011-12-12
申请人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/105 , H01L21/336
CPC分类号： H01L21/84 , H01L27/0629 , H01L27/1203 , H01L27/1207 , H01L27/13 , H01L28/10 , H01L29/8611 , H01L29/94
摘要： An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
摘要翻译：通过在替换栅极HK / MG流中蚀刻ETSOI和BOX层，在其晶体管和电容器区域中分别形成ETSOI晶体管以及电容器，结二极管，堤端触点和电阻器的组合。电容器和其他器件形成与ETSOI替代栅极CMOS流相兼容。低电阻电容器电极可以获得高质量的电容器和器件。虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。

37. 发明授权

US08445971B2 Field effect transistor device with raised active regions 有权
标题翻译：场效应晶体管器件具有凸起的有源区
公开(公告)号：US08445971B2
公开(公告)日：2013-05-21
申请号：US13237319
申请日：2011-09-20
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/41775 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面，第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

38. 发明申请

US20120295417A1 SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING 审中-公开
标题翻译：选择性外来成长通过孵化时间工程
公开(公告)号：US20120295417A1
公开(公告)日：2012-11-22
申请号：US13109567
申请日：2011-05-17
申请人： Thomas N. Adam , Katherina E. Babich , Stephen W. Bedell , Joel P. de Souza , Gerald W. Gibson , Alexander Reznicek , Devendra K. Sadana , Seshadri Subbanna
发明人： Thomas N. Adam , Katherina E. Babich , Stephen W. Bedell , Joel P. de Souza , Gerald W. Gibson , Alexander Reznicek , Devendra K. Sadana , Seshadri Subbanna
IPC分类号： H01L21/20
CPC分类号： H01L29/66628 , H01L21/0237 , H01L21/02524 , H01L21/02639 , H01L29/165 , H01L29/78
摘要： A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.
摘要翻译：提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率，或通过改变掩模层的表面以获得适当的成核特性。或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

39. 发明授权

US08288217B2 Stressor in planar field effect transistor device 失效
标题翻译：应力平面场效应晶体管器件
公开(公告)号：US08288217B2
公开(公告)日：2012-10-16
申请号：US12945026
申请日：2010-11-12
申请人： Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Alexander Reznicek , Keith Kwong Hon Wong
发明人： Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Alexander Reznicek , Keith Kwong Hon Wong
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/1054 , H01L29/66477 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.
摘要翻译：场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

40. 发明授权

US08263468B2 Thin body semiconductor devices 有权
标题翻译：薄体半导体器件
公开(公告)号：US08263468B2
公开(公告)日：2012-09-11
申请号：US12766859
申请日：2010-04-24
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/66795 , H01L29/78696
摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.
摘要翻译：公开了一种用于制造FET器件的方法。该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。选择身体为Si，Ge或其合金混合物。选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

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