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31. 发明申请

US20120213290A1 Parallel video decoding 审中-公开
标题翻译：并行视频解码
公开(公告)号：US20120213290A1
公开(公告)日：2012-08-23
申请号：US13317466
申请日：2011-10-19
申请人： Ola Hugosson , Dominic Hugo Symes
发明人： Ola Hugosson , Dominic Hugo Symes
IPC分类号： H04N7/26 , H04N7/30 , H04N7/32
CPC分类号： H04N19/436 , H04N19/30 , H04N19/33
摘要： A video decoding apparatus and method are disclosed. The video decoding apparatus comprises at least one parsing unit configured to receive input video data as an encoded video bitstream which contains sequential internal dependencies. The at least one parsing unit is configured to perform a parsing operation on the encoded video bitstream to generate an intermediate representation of the input video data in which at least a subset of the sequential internal dependencies are resolved. The intermediate representation of the input video data can be stored in a buffer. The video decoding apparatus further comprises a reconstruction unit configured to retrieve in parallel a plurality of input streams of the intermediate representation and to perform a decoding operation on the plurality of input streams in parallel to generate decoded output video data.
摘要翻译：公开了一种视频解码装置和方法。视频解码装置包括至少一个解析单元，其被配置为接收作为包含顺序内部依赖性的编码视频比特流的输入视频数据。所述至少一个解析单元被配置为对编码的视频比特流执行解析操作以生成输入视频数据的中间表示，其中顺序内部依赖关系的至少一个子集被解析。输入视频数据的中间表示可以存储在缓冲器中。视频解码装置还包括重构单元，被配置为并行地检索中间表示的多个输入流，并且对多个输入流并行地执行解码操作，以产生解码的输出视频数据。

32. 发明授权

US08200948B2 Apparatus and method for performing re-arrangement operations on data 有权
标题翻译：对数据执行重新排列操作的装置和方法
公开(公告)号：US08200948B2
公开(公告)日：2012-06-12
申请号：US11987720
申请日：2007-12-04
申请人： Daniel Kershaw , Dominic Hugo Symes , Alastair Reid
发明人： Daniel Kershaw , Dominic Hugo Symes , Alastair Reid
IPC分类号： G06F7/38 , G06F9/30 , G06F9/302 , G06F15/80
CPC分类号： G06F9/30032 , G06F9/30036
摘要： An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and processing logic for performing a sequence of operations on data including at least one re-arrangement operation. The processing logic has scalar processing logic for performing scalar operations and SIMD processing logic for performing SIMD operations. The SIMD processing logic is responsive to a re-arrangement instruction specifying a family of re-arrangement operations to perform a selected re-arrangement operation from that family on a plurality of data elements constituted by data in one or more registers identified by the re-arrangement instruction. The selected re-arrangement operation is dependent on at least one parameter provided by the scalar processing logic, that parameter identifying a data element width for the data elements on which the selected re-arrangement operation is performed. By such an approach, significant code density improvements can be made in respect of the code executed by the SIMD processing logic.
摘要翻译：提供了一种用于对数据执行重新排列操作的装置和方法。数据处理装置具有一个具有多个用于存储数据的寄存器的寄存器数据存储器，以及用于对包括至少一个重新布置操作的数据执行一系列操作的处理逻辑。处理逻辑具有用于执行标量操作和用于执行SIMD操作的SIMD处理逻辑的标量处理逻辑。 SIMD处理逻辑响应于指定一系列重新布置操作的重新布置指令，以便在由重新配置操作确定的一个或多个寄存器中的数据构成的多个数据元素上从该系列执行所选择的重新排列操作，安排指导。所选择的重新布置操作取决于由标量处理逻辑提供的至少一个参数，该参数标识用于执行所选重新布置操作的数据元素的数据元素宽度。通过这种方法，可以对由SIMD处理逻辑执行的代码进行显着的代码密度改进。

33. 发明申请

US20110106871A1 Apparatus and method for performing multiply-accumulate operations 有权
标题翻译：用于执行多重累加操作的装置和方法
公开(公告)号：US20110106871A1
公开(公告)日：2011-05-05
申请号：US12926171
申请日：2010-10-29
申请人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
发明人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
IPC分类号： G06F7/544 , G06F7/52
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.
摘要翻译：提供了一种用于执行多重累加操作的数据处理装置和方法。数据处理装置包括响应于控制信号的数据处理电路，以对至少一个输入数据元素执行数据处理操作。指令解码器电路响应于指定作为输入操作数的第一输入数据元素，第二输入数据元素和谓词值的预测乘法累加指令，以产生控制信号以控制数据处理电路执行乘法累加操作通过：将所述第一输入数据元素和所述第二输入数据元素相乘以产生乘法数据元素; 如果谓词值具有第一值，则通过将乘数据元素添加到初始累加数据元素来产生结果累积数据元素; 并且如果谓词值具有第二值，则通过从初始累加数据元素中减去乘法数据元素来产生结果累积数据元素。这种方法提供了一种特别有效的机制，用于执行乘法和乘法运算的复杂序列，与已知的现有技术相比，有助于提高性能，能量消耗和代码密度。

34. 发明申请

US20100274990A1 Apparatus and Method for Performing SIMD Multiply-Accumulate Operations 有权
标题翻译：用于执行SIMD乘法运算的装置和方法
公开(公告)号：US20100274990A1
公开(公告)日：2010-10-28
申请号：US12585573
申请日：2009-09-17
申请人： Mladen Wilder , Dominic Hugo Symes , Richard Edward Bruce
发明人： Mladen Wilder , Dominic Hugo Symes , Richard Edward Bruce
IPC分类号： G06F15/76 , G06F9/302 , G06F9/02 , G06F9/30
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30065 , G06F9/3893
摘要： An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes.
摘要翻译：用于执行SIMD乘法累加操作的装置和方法包括响应于控制信号的SIMD数据处理电路，以对多个数据元素并行地执行数据处理操作。指令解码器电路耦合到SIMD数据处理电路，并且响应于程序指令以产生所需的控制信号。指令解码器电路响应于具有作为输入操作数的输入数据元素的第一向量，系数数据元素的第二向量和指示多个的标量值的单个指令（这里称为重复乘法累加指令）以产生控制信号以控制SIMD处理电路。响应于这些控制信号，SIMD数据处理电路执行多次累积处理的多次迭代，每次迭代涉及并行执行N次乘法运算，以产生N个乘法累加数据元素。对于每次迭代，SIMD数据处理电路从所述第一向量确定N个输入数据元素，并且从第二向量确定要与N个输入数据元素中的每一个相乘的单个系数数据元素。然后，在乘法累加过程的最终迭代中产生的N个乘法累加数据元素用于产生N个乘法累加结果。该机制提供了用于执行SIMD乘法累加操作的特别高效的机制，例如FIR滤波器处理所需要的。

35. 发明申请

US20100106944A1 Data processing apparatus and method for performing rearrangement operations 有权
标题翻译：用于执行重排操作的数据处理装置和方法
公开(公告)号：US20100106944A1
公开(公告)日：2010-04-29
申请号：US12588412
申请日：2009-10-14
申请人： Dominic Hugo Symes , Simon Andrew Ford
发明人： Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30189 , G06F9/345 , G06F9/382 , G06F9/3832 , G06F9/3873 , G06F9/3887 , G06F2207/3828
摘要： A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.
摘要翻译：提供了一种执行重排操作的数据处理装置和方法。数据处理装置具有具有多个寄存器的寄存器数据存储器，每个寄存器存储多个数据元素。处理电路响应于控制信号来对数据元素执行处理操作。指令解码器响应于至少一个但不超过N个重排指令，其中N是奇数复数，以产生控制信号，以控制处理电路执行至少等同于：作为源数据元素的重新排列过程存储在由所述至少一个重新布置指令识别的所述寄存器数据存储器的N个寄存器中的数据元素; 执行重排操作以在常规N路交错顺序和解交织顺序之间重新排列源数据元素，以便产生结果数据元素的序列; 并输出用于存储在寄存器数据存储器中的结果数据元素的序列。这提供了一种特别有效的技术，用于执行N路交错和解交织操作，其中N是奇数，导致高性能，低能量消耗和降低的寄存器使用，与已知的现有技术相比。

36. 发明申请

US20080229073A1 Address calculation and select-and insert instructions within data processing systems 有权
标题翻译：地址计算和数据处理系统中的选择和插入指令
公开(公告)号：US20080229073A1
公开(公告)日：2008-09-18
申请号：US12068903
申请日：2008-02-13
申请人： Dominic Hugo Symes , Daniel Kershaw , Mladen Wilder
发明人： Dominic Hugo Symes , Daniel Kershaw , Mladen Wilder
IPC分类号： G06F9/30
CPC分类号： H03M13/4169 , G06F9/30036 , G06F9/345 , G06F9/355 , G06F9/3885 , G06F9/3887 , H04L1/0052 , H04L1/0054
摘要： A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value. The address calculation instruction and the select-and-insert instruction described above are useful when manipulating two-dimensional data arrays, and particularly so when these are two-dimensional data arrays are formed of Viterbi trellis data through which traceback operations are to be performed.
摘要翻译：提供数据处理系统2，其包括响应于指令寄存器32内的程序指令的指令解码器34，以产生用于控制数据处理电路36的控制信号。所支持的指令包括地址计算指令，其将位置相关的输入地址值分割在将尺寸值分配到第一部分和第二部分中时，向第一部分添加非零偏移值，将第二部分设置为值，然后将处理结果连接在第一部分和第二部分上，以形成输出地址值。支持的另一种类型的指令是选择和插入指令。该指令采用第一输入值并将其移位N位位置以形成移位值，根据第一输入值从第二输入值内选择N位，然后将移位值与N位相连以形成输出值。上述地址计算指令和选择和插入指令在操纵二维数据阵列时非常有用，特别是当这些二维数据阵列由维特比网格数据形成时，通过该数据将执行回溯操作。

37. 发明授权

US07370210B2 Apparatus and method for managing processor configuration data 有权
标题翻译：用于管理处理器配置数据的装置和方法
公开(公告)号：US07370210B2
公开(公告)日：2008-05-06
申请号：US10713303
申请日：2003-11-17
申请人： Dominic Hugo Symes
发明人： Dominic Hugo Symes
IPC分类号： G06F11/30 , G06F11/00 , H04L9/00 , H04K1/00
CPC分类号： G06F9/4812
摘要： The present invention provides a data processing apparatus and method for managing processor configuration data. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain, at least one secure mode being a mode in the secure domain, and a monitor mode. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when said processor is operating in a non-secure mode. A storage unit is used to store processor configuration data, and the processor is operable at least partially in the monitor mode to execute a monitor program to manage switching between the secure domain and the non-secure domain, the switching including switching the processor configuration data in the storage unit between secure processor configuration data and non-secure processor configuration data. When in the monitor mode, the monitor program is operable to use monitor mode specific processor configuration data, thereby ensuring that operation of the processor in the monitor mode is unaffected by the switching of the processor configuration data.
摘要翻译：本发明提供一种用于管理处理器配置数据的数据处理装置和方法。数据处理装置包括可以多个模式操作的处理器和多个域，所述多个域包括安全域和非安全域，所述多个模式包括至少一个非安全模式非安全域，至少一个安全模式是安全域中的模式，以及监视模式。处理器是可操作的，使得当以安全模式执行程序时，程序可以访问当所述处理器以非安全模式操作时不可访问的安全数据。存储单元用于存储处理器配置数据，并且处理器可至少部分地以监视模式操作，以执行监视程序来管理安全域与非安全域之间的切换，切换包括切换处理器配置数据在存储单元中的安全处理器配置数据和非安全处理器配置数据之间。当处于监视器模式时，监视程序可操作以使用监视模式特定的处理器配置数据，从而确保处于监视模式的处理器的操作不受处理器配置数据的切换的影响。

38. 发明授权

US06958718B2 Table lookup operation within a data processing system 有权
公开(公告)号：US06958718B2
公开(公告)日：2005-10-25
申请号：US10889217
申请日：2004-07-13
申请人： Dominic Hugo Symes , Simon Ford , Andrew Christopher Rose
发明人： Dominic Hugo Symes , Simon Ford , Andrew Christopher Rose
IPC分类号： G06F9/38 , G06F7/00 , G06F9/00 , G06F9/30 , G06F9/305 , G06F9/312 , G06F9/318 , G06F9/35 , G06F9/355 , H03M7/00
CPC分类号： G06F9/3004 , G06F9/30181 , G06F9/342 , G06F9/383
摘要： A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations within the result register being left unchanged U. In this way, an offset can be applied to index values held and then those index values reused with the table registers D0, D1 being reloaded with a different portion of a table so as to give the effect of a larger table than can be directly supported by the number of table registers available.

39. 发明授权

US06831952B2 System, method and computer program for decoding an encoded data stream 失效
标题翻译：用于解码编码数据流的系统，方法和计算机程序
公开(公告)号：US06831952B2
公开(公告)日：2004-12-14
申请号：US09799878
申请日：2001-03-07
申请人： Dominic Hugo Symes , Hedley James Francis
发明人： Dominic Hugo Symes , Hedley James Francis
IPC分类号： H04L2700
CPC分类号： G11B20/10296 , G11B20/12 , H03M13/39 , H03M13/41 , H03M13/4107
摘要： A technique for decoding an encoded data stream representing an original sequence of data bits, each data bit comprising a plurality of codes, each code being dependent on a current data bit and a first predetermined number of preceding data bits in the original sequence. Scores are provided indicating the likelihood that a corresponding state represents the first predetermined number of preceding data bits. The scores are arranged in an initial ordering. A first plurality of score bit slices are stored to collectively represent the initially ordered scores, each score bit slice containing a predetermined bit from each of the scores. The scores are then reordered and a second plurality of score bit slices are stored to collectively represent the reordered scores. By this approach, all the scores are updated simultaneously.
摘要翻译：一种用于解码表示原始数据位序列的编码数据流的技术，每个数据位包括多个代码，每个代码取决于原始序列中的当前数据位和第一预定数量的先前数据位。提供表示指示对应状态表示第一预定数量的先前数据位的可能性。分数按初始排序排列。存储第一多个分数比特片以共同表示最初排序的分数，每个分数比特片包含来自每个分数的预定比特。然后重新排序分数，并且存储第二多个分数比特片以共同表示重新排序的分数。通过这种方法，所有得分都被同时更新。

40. 发明授权

US10165291B2 Parallel parsing in a video decoder 有权
公开(公告)号：US10165291B2
公开(公告)日：2018-12-25
申请号：US12929639
申请日：2011-02-04
申请人： Ola Hugosson , Dominic Hugo Symes
发明人： Ola Hugosson , Dominic Hugo Symes
IPC分类号： H04N19/436 , H04N19/172 , H04N19/44
摘要： A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit.

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