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31. 发明授权

US07027347B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07027347B2
公开(公告)日：2006-04-11
申请号：US10749510
申请日：2004-01-02
申请人： Kenichi Shigenami , Shunichi Sukegawa
发明人： Kenichi Shigenami , Shunichi Sukegawa
IPC分类号： G11C8/00
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C8/12 , G11C11/4082 , G11C11/4096 , G11C2207/2245
摘要： A semiconductor memory device for improving the utilization of a shared data bus and the data transfer rate in a multi-bank DRAM and realizing high speed data accessing without increasing a scale of a control circuit, wherein the multi-bank DRAM has memory banks provided with an address register for holding a write address, a data register for holding write data, an address matching detection circuit for detecting whether an address held in the address register matches with an address input this time, and when reading is performed continuously from writing on the same address of the same memory bank, reading is not performed on a memory cell specified by a read address and data held in the data register is output as read data, so that memory accessing made continuously to the same address can be performed at a high speed.
摘要翻译：一种半导体存储器件，用于改善共享数据总线的利用率和数据传输速率，并且在不增加控制电路规模的情况下实现高速数据访问，其中多存储体DRAM具有提供有存储器用于保持写入地址的地址寄存器，用于保持写入数据的数据寄存器，用于检测保持在地址寄存器中的地址是否与此时输入的地址一致的地址匹配检测电路，相同存储体的相同地址，读取不是由读取地址指定的存储单元执行，数据寄存器中保存的数据作为读取数据输出，从而能够以高位执行对连续地进行相同地址的存储器访问速度。

32. 发明授权

US5805522A Address access path control circuit 失效
标题翻译：地址访问路径控制电路
公开(公告)号：US5805522A
公开(公告)日：1998-09-08
申请号：US706373
申请日：1996-08-30
申请人： Shunichi Sukegawa , Koichi Abe , Makoto Saeki , Yukihide Suzuki
发明人： Shunichi Sukegawa , Koichi Abe , Makoto Saeki , Yukihide Suzuki
IPC分类号： G11C11/413 , G11C7/10 , G11C11/401 , G11C11/408 , G11C11/409 , G11C8/00 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： An address access path control circuit designed for shorter access time and small the layout area with low power consumption and noise. Our control circuit has a latching circuit LMO2A, a main output circuit MO3, and a common-bus driving circuit CBD for holding the level of a pair of common-buses CB/CB.sub.-- at the ground level during a prescribed period of time in which address transition takes place while the read data is output to common-buses CB/CB.sub.-- at a timing corresponding to the address signal. A data output buffer DO-BUF outputs to the outside the data transmitted from common-buses CB/CB.sub.-- to data output lines OD/OD.sub.-- in response to the input of control signal DOE. A control signal DOE is input to data output buffer DO-BUF during the period in which data output lines OD/OD.sub.-- are at the ground level.
摘要翻译：一种地址访问路径控制电路，设计用于更短的访问时间，并且具有低功耗和噪声的布局区域较小。我们的控制电路有一个锁存电路LMO2A，一个主输出电路MO3和一个共用总线驱动电路CBD，用于在一段规定的时间内保持一对公共汽车CB / CB-的电平，在与地址信号相对应的定时将读取数据输出到公共总线CB / CB-时发生地址转换。响应于控制信号DOE的输入，数据输出缓冲器DO-BUF向外部输出从公共总线CB / CB-发送到数据输出线OD / OD-的数据。在数据输出线OD / OD-处于地电平的期间，控制信号DOE输入到数据输出缓冲器DO-BUF。

33. 发明授权

US5596535A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US5596535A
公开(公告)日：1997-01-21
申请号：US267267
申请日：1994-06-28
申请人： Tathunori Mushya , Masayasu Kawamura , Shunichi Sukegawa
发明人： Tathunori Mushya , Masayasu Kawamura , Shunichi Sukegawa
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , G11C7/00 , G11C8/00
CPC分类号： G11C29/80 , G11C29/84
摘要： A semiconductor storage device equipped with redundant circuits designed to increase the operating speed and to simplify the layout by providing for the detection of the storage of a faulty address and access to the faulty address so as to substitute a spare word line for a faulty word line. The semiconductor storage device includes a MOSFET for causing current to flow through a pair of fuse means by a complementary address signal at one end of a fuse means corresponding to each bit of the faulty address. The other end thereof is connected to a wired OR logic so as to generate a decision signal. The fuse means corresponding to the MOSFET which is turned on by the faulty address signal is cut off to store a faulty address. The faulty address storage and comparison units can be formed with the pair of fuses and the MOSFET. High-speed operation and a high-density layout in the form of a matrix can thus be achieved efficiently by switching the faulty circuit to a spare circuit while the normal decoder is operating.
摘要翻译：一种装备有冗余电路的半导体存储装置，其设计用于通过提供对故障地址的存储的检测和对故障地址的访问来提高操作速度和简化布局，以便将备用字线替换为有缺陷的字线。半导体存储装置包括用于使电流通过对应于故障地址的每个位的熔丝装置的一端的互补地址信号流过一对熔丝装置的MOSFET。其另一端连接到有线OR逻辑，以产生判定信号。对应于通过故障地址信号导通的MOSFET的熔丝装置被切断以存储故障地址。故障地址存储和比较单元可以由一对保险丝和MOSFET形成。因此，在通常的解码器工作时，通过将故障电路切换到备用电路，能够有效地实现矩阵形式的高速运转和高密度布局。

34. 发明授权

US5550394A Semiconductor memory device and defective memory cell correction circuit 失效
标题翻译：半导体存储器件和缺陷存储单元校正电路
公开(公告)号：US5550394A
公开(公告)日：1996-08-27
申请号：US80159
申请日：1993-06-18
申请人： Shunichi Sukegawa , Takumi Nasu , Hidetoshi Iwai
发明人： Shunichi Sukegawa , Takumi Nasu , Hidetoshi Iwai
IPC分类号： G11C29/00 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： G11C29/78 , G11C29/785 , G11C29/84 , G11C29/781
摘要： To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.
摘要翻译：提供一种半导体存储器件，其特征在于它可以防止由熔丝解码器中的熔丝的固有电阻引起的冗余存储器地址一致信号产生电路中的错误，并且它具有用于产生高速地址的冗余机制巧合信号。它具有由门输出可编程的多个逻辑门装置和保险丝。每个保险丝的输出信号被连线以产生地址一致信号。

35. 发明申请

US20130062504A1 SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND CAMERA SYSTEM 审中-公开
标题翻译：半导体器件，固态成像器件和摄像机系统
公开(公告)号：US20130062504A1
公开(公告)日：2013-03-14
申请号：US13697167
申请日：2011-05-26
申请人： Shunichi Sukegawa , Noriyuki Fukushima
发明人： Shunichi Sukegawa , Noriyuki Fukushima
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14618 , H01L23/481 , H01L23/49827 , H01L27/14634 , H01L27/14683 , H01L27/1469 , H01L2224/13 , H01L2924/13091 , H01L2924/00
摘要： Disclosed herein is a solid state imaging device including a support substrate; an imaging semiconductor chip having a pixel array disposed on the support substrate; and an image processing semiconductor chip disposed on the support substrate, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected by through-vias, and interconnects formed on the support substrate.
摘要翻译：本文公开了包括支撑基板的固态成像装置; 具有设置在所述支撑基板上的像素阵列的成像半导体芯片; 以及设置在所述支撑基板上的图像处理半导体芯片，其中所述成像半导体芯片和所述图像处理半导体芯片通过通孔连接，以及形成在所述支撑基板上的互连。

36. 发明授权

US07995966B2 Communication semiconductor chip, calibration method, and program 失效
标题翻译：通信半导体芯片，校准方法和程序
公开(公告)号：US07995966B2
公开(公告)日：2011-08-09
申请号：US11554817
申请日：2006-10-31
申请人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
发明人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
IPC分类号： H04B7/00
CPC分类号： H05K1/141 , H01L25/0652 , H01L25/18 , H01L2224/16225 , H01L2924/01019 , H01L2924/01037 , H01L2924/19107 , H05K1/0243 , H05K1/144 , H05K3/284 , H05K2201/045 , H05K2201/10098 , H05K2201/10515 , H05K2201/10674
摘要： A communication semiconductor chip performs wireless communication with another communication semiconductor chip. The semiconductor chip includes a communication module and a control unit. The communication module performs the wireless communication with another communication semiconductor chip and has a receiving circuit for receiving data. The control unit supplies a reference voltage to the receiving circuit and performs a calibration operation on the reference voltage.
摘要翻译：通信半导体芯片与另一通信半导体芯片进行无线通信。半导体芯片包括通信模块和控制单元。通信模块与另一通信半导体芯片进行无线通信，并具有用于接收数据的接收电路。控制单元向接收电路提供参考电压，并对参考电压进行校准操作。

37. 发明授权

US07712663B2 Communication board 有权
标题翻译：通讯板
公开(公告)号：US07712663B2
公开(公告)日：2010-05-11
申请号：US11473160
申请日：2006-06-23
申请人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
发明人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
IPC分类号： G06K7/08
CPC分类号： H01L23/538 , H01L23/49838 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2223/6677 , H01L2225/06527 , H01L2924/0002 , H01L2924/19015 , H01L2924/3011 , H01Q1/2258 , H01Q1/241 , H01Q7/00 , H04B5/02 , H01L2924/00
摘要： A communication board mounted on an electronic device includes a plurality of antennas configured to transmit and/or receive a signal by electromagnetic induction, where each of the plurality of antennas is provided on a substrate, as a coil-shaped pattern, a semiconductor chip mounted on the substrate, the semiconductor chip including at least one of a transmission circuit which transmits a signal to the antenna and a reception circuit which receives a signal transmitted from the antenna, and an input-and-output end that is connected to the semiconductor chip via a wiring layer provided on the substrate and an electronic circuit of the electronic device. The communication board communicates with a communication board mounted on another electronic device via the antenna by electromagnetic induction.
摘要翻译：安装在电子设备上的通信板包括配置成通过电磁感应传输和/或接收信号的多个天线，其中多个天线中的每一个设置在基板上，作为线圈形图案，安装有半导体芯片在基板上，包括将信号发送到天线的发送电路和接收从天线发送的信号的接收电路中的至少一个的半导体芯片和连接到半导体芯片的输入输出端通过设置在基板上的布线层和电子设备的电子电路。通信板通过电磁感应通过天线与安装在另一电子设备上的通信板进行通信。

38. 发明授权

US07400038B2 Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip for communication 失效
标题翻译：半导体装置，基板，设备基板，半导体装置的制造方法以及通信用半导体芯片
公开(公告)号：US07400038B2
公开(公告)日：2008-07-15
申请号：US11202180
申请日：2005-08-12
申请人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
发明人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
IPC分类号： H01L23/34
CPC分类号： H01L23/66 , H01L23/48 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/105 , H01L25/162 , H01L25/18 , H01L2223/6677 , H01L2224/16 , H01L2224/4824 , H01L2224/48247 , H01L2224/4943 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/1627 , H01L2924/181 , H01L2924/3025 , H01Q7/00 , H01Q21/061 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.
摘要翻译：半导体器件包括具有用于安装电子部件的第一表面和基本上平行于第一表面的第二表面的第一基板。第一基板包括用于安装电子部件的第一区域，包括用于向第二基板发送信号和从第二基板发送信号的多个第一通信单元的第二区域，设置在第一区域或第二区域上的输入输出电路，对应于第一通信单元的输入输出电路，以及控制电路，用于控制从设置在第一基板的第一区域或第二区域上的输入输出电路的输入和输出。每个输入输出电路包括用于向与第一通信单元相对应的第二基板的第二通信单元输出信号的输出电路和用于接收从相应的第二通信单元发送的信号的输入单元。

39. 发明申请

US20070001270A1 Communication board 有权
标题翻译：通讯板
公开(公告)号：US20070001270A1
公开(公告)日：2007-01-04
申请号：US11473160
申请日：2006-06-23
申请人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
发明人： Shunichi Sukegawa , Takeo Sekino , Kenichi Shigenami , Shinichi Toi , Tatsuo Shimizu
IPC分类号： H01L23/58 , H03K3/00
CPC分类号： H01L23/538 , H01L23/49838 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2223/6677 , H01L2225/06527 , H01L2924/0002 , H01L2924/19015 , H01L2924/3011 , H01Q1/2258 , H01Q1/241 , H01Q7/00 , H04B5/02 , H01L2924/00
摘要： A communication board mounted on an electronic device includes a plurality of antennas configured to transmit and/or receive a signal by electromagnetic induction, where each of the plurality of antennas is provided on a substrate, as a coil-shaped pattern, a semiconductor chip mounted on the substrate, the semiconductor chip including at least one of a transmission circuit which transmits a signal to the antenna and a reception circuit which receives a signal transmitted from the antenna, and an input-and-output end that is connected to the semiconductor chip via a wiring layer provided on the substrate and an electronic circuit of the electronic device. The communication board communicates with a communication board mounted on another electronic device via the antenna by electromagnetic induction.
摘要翻译：安装在电子设备上的通信板包括配置成通过电磁感应传输和/或接收信号的多个天线，其中多个天线中的每一个设置在基板上，作为线圈形图案，安装有半导体芯片在基板上，包括将信号发送到天线的发送电路和接收从天线发送的信号的接收电路中的至少一个的半导体芯片和连接到半导体芯片的输入输出端通过设置在基板上的布线层和电子设备的电子电路。通信板通过电磁感应通过天线与安装在另一电子设备上的通信板进行通信。

40. 发明授权

US06265907B1 Signal transmission circuit having intermediate amplifier circuit 失效
标题翻译：信号传输电路具有中间放大电路
公开(公告)号：US06265907B1
公开(公告)日：2001-07-24
申请号：US09053365
申请日：1998-04-01
申请人： Shunichi Sukegawa
发明人： Shunichi Sukegawa
IPC分类号： H03L522
CPC分类号： G11C7/065 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078
摘要： A signal transmission circuit which enables the distance of signal transmission to be increased, while the signal delay and power consumption are reduced. The signal transmission circuit includes a driver circuit, a receiver circuit, an equalizer circuit that flattens the output of the driver circuit, and an intermediate amplifier circuit. The intermediate amplifier circuit is connected to input/output shared terminals in the wiring that connects the driver circuit and the receiver circuit. With the aid of the positive feedback of the intermediate amplifier circuit, a differential signal output from the driver circuit is amplified and then transmitted to the receiver circuit.
摘要翻译：信号传输电路能够在信号延迟和功耗降低的同时增加信号传输的距离。信号传输电路包括驱动电路，接收器电路，使驱动电路的输出变平的均衡器电路和中间放大器电路。中间放大器电路连接到连接驱动电路和接收电路的布线中的输入/输出共用端子。借助于中间放大器电路的正反馈，从驱动电路输出的差分信号被放大然后传输到接收器电路。

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