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31. 发明申请

US20100223531A1 SEMICONDUCTOR STORAGE 失效
标题翻译：半导体存储
公开(公告)号：US20100223531A1
公开(公告)日：2010-09-02
申请号：US12713631
申请日：2010-02-26
申请人： Kazuhiro FUKUTOMI , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro FUKUTOMI , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
IPC分类号： H03M13/05 , G06F12/16 , G06F11/10
CPC分类号： G06F11/108 , G06F11/1052
摘要： A semiconductor storage includes a receiver configured to receive a write request from a host device; a storage unit configured to hold redundancy data generation/non-generation information; a writing unit configured to write data in a semiconductor memory array and write redundancy data generation/non-generation information of the written data in the storage unit; a first data extracting unit configured to extract data whose redundancy data is not generated from among the data held by the semiconductor memory array; a first redundancy data generating unit configured to generate redundancy data; a first redundancy data writing unit configured to write the generated redundancy data in the semiconductor memory array; and a first redundancy data generation/non-generation information updating unit configured to update the redundancy data generation/non-generation information of the data whose redundancy data held by the storage unit is generated.
摘要翻译：半导体存储器包括被配置为从主机设备接收写请求的接收器; 存储单元，被配置为保存冗余数据生成/非生成信息; 写入单元，被配置为在半导体存储器阵列中写入数据，并将写入的数据的冗余数据生成/非生成信息写入存储单元中; 第一数据提取单元，被配置为从半导体存储器阵列保存的数据中提取不产生冗余数据的数据; 第一冗余数据生成单元，被配置为生成冗余数据; 第一冗余数据写入单元，被配置为将所生成的冗余数据写入所述半导体存储器阵列中; 以及第一冗余数据生成/非生成信息更新单元，被配置为更新由所述存储单元保持的冗余数据生成的数据的冗余数据生成/非生成信息。

32. 发明授权

US07733122B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07733122B2
公开(公告)日：2010-06-08
申请号：US12369522
申请日：2009-02-11
申请人： Takashi Yoshikawa , Shigehiro Asano
发明人： Takashi Yoshikawa , Shigehiro Asano
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F15/7867 , G06F9/30156 , G06F9/30178 , G06F9/30181
摘要： A first operation unit stores first code information having a bit length shorter than a first set bit, receives dictionary information expressing each set bit corresponding to each code information, reads the set bit corresponding to the first code information from the dictionary information to obtain the first set bit, and further, changes setting according to the first set bit to execute any of a plurality of operations so as to obtain an operation result. A second operation unit stores second code information having a bit length shorter than a second set bit, receives the dictionary information from the first operation unit, reads the set bit corresponding to the second code information from the dictionary information to obtain the second set bit, and further, changes setting according to the second set bit so as to execute any of the operations with respect to the operation result.
摘要翻译：第一操作单元存储具有比第一设置位短的位长度的第一代码信息，接收表示与每个代码信息相对应的每个设置位的字典信息，从字典信息读取与第一代码信息对应的设置位，以获得第一代码信息并且进一步根据第一设置位改变设置以执行多个操作中的任一个以获得操作结果。第二操作单元存储具有比第二设定位短的位长度的第二代码信息，从第一操作单元接收字典信息，从字典信息读取对应于第二代码信息的设置位，以获得第二设置位，并且进一步根据第二设置位进行改变设置，以便执行关于操作结果的任何操作。

33. 发明申请

US20100037012A1 Semiconductor Storage Device, Method of Controlling the Same, Controller and Information Processing Apparatus 失效
标题翻译：半导体存储装置及其控制方法，控制器及信息处理装置
公开(公告)号：US20100037012A1
公开(公告)日：2010-02-11
申请号：US12552461
申请日：2009-09-02
申请人： Hirokuni Yano , Shinichi Kanno , Toshikatsu Hida , Hidenori Matsuzaki , Kazuya Kitsunai , Shigehiro Asano
发明人： Hirokuni Yano , Shinichi Kanno , Toshikatsu Hida , Hidenori Matsuzaki , Kazuya Kitsunai , Shigehiro Asano
IPC分类号： G06F12/02
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0656 , G06F3/0658 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7209 , G11C11/5628
摘要： A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit from the fourth memory area to the second memory area, a fifth processing for copying data to an area of the third unit and allocating the area to the second memory area, and a sixth processing for copying data to an empty area of the third unit in the second memory area.
摘要翻译：半导体存储装置包括配置在非易失性半导体存储器中的易失性半导体存储器，第二，第三和第四存储区域中的第一存储区域和执行以下处理的控制器。控制器执行第一处理，用于将第一单元存储在第一存储区域中的多个数据，第二处理，用于由第一管理单元存储在第四存储区域中的数据;第三处理，用于由第二管理单元存储数据在第三存储区域中，用于将第三单元的区域从第四存储区域移动到第二存储区域的第四处理，用于将数据复制到第三单元的区域并将区域分配给第二存储区域的第五处理以及用于将数据复制到第二存储区域中的第三单元的空白区域的第六处理。

34. 发明授权

US07373444B2 Systems and methods for manipulating entries in a command buffer using tag information 失效
标题翻译：使用标签信息来处理命令缓冲区中的条目的系统和方法
公开(公告)号：US07373444B2
公开(公告)日：2008-05-13
申请号：US11106791
申请日：2005-04-15
申请人： Shigehiro Asano , Tsutomu Ishii
发明人： Shigehiro Asano , Tsutomu Ishii
IPC分类号： G06F13/00
CPC分类号： G06F13/42
摘要： Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master devices and multiple slave devices are coupled to a split transaction bus. When a read command is received by a target slave device, the slave device generates an acknowledgment if the slave's command buffer has available entries, or a retry reply if the slave's command buffer is full. The acknowledgment includes a tag which is an index to the buffer location in which the command is stored. If a combined response to the command which is received by the slave device is a retry, the tag, which is included therein, is used by the slave to clear the command from its command buffer.
摘要翻译：用于促进在缓冲器中的条目的位置的系统和方法，其中从设备存储与活动事务相关的信息，使得如果对应的事务被取消，则可以移除条目。在一个实施例中，多个主设备和多个从设备耦合到分离事务总线。当目标从设备接收到读命令时，如果从站的命令缓冲区有可用条目，则从站设备生成一个确认，或者如果从站的命令缓冲区已满，则重试应答。该确认包括作为其中存储命令的缓冲器位置的索引的标签。如果对由从设备接收到的命令的组合响应是重试，则被包括在其中的标签被从机用来从其命令缓冲器中清除该命令。

35. 发明申请

US20070245131A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20070245131A1
公开(公告)日：2007-10-18
申请号：US11727134
申请日：2007-03-23
申请人： Takashi Yoshikawa , Shigehiro Asano , Yutaka Yamada
发明人： Takashi Yoshikawa , Shigehiro Asano , Yutaka Yamada
IPC分类号： G06F15/00
CPC分类号： G06F15/7867
摘要： A semiconductor device for performing data processing by performing a plurality of computations in cycles includes a pipeline formed by connecting a plurality of computing units in series, each of the computing units including: a data line for receiving data; a control line for receiving a rule signal; a circuit information control unit configured to store, before data processing, several circuit information items, and to output a first one of the several circuit information items according to the rule signal received via the control line in a first cycle of the data processing; a processing element configured to construct an execution circuit according to the first circuit information item, to perform a computation using data from the data line, and to output a computation result; a data register for storing the computation result, and for outputting the computation result in a second cycle; and a control register for storing the rule signal and for outputting the rule signal in the second cycle. The semiconductor further includes a controller configured to control output timing of the rule signal to the control line of a first-stage one of the computing units in the pipeline and to control output timing of the data to the data line of the first-stage computing unit in the first cycle, so that the plurality of computing units are operated as a pipeline.
摘要翻译：用于通过循环执行多个计算来执行数据处理的半导体装置包括通过串联连接多个计算单元而形成的流水线，每个计算单元包括：用于接收数据的数据线; 用于接收规则信号的控制线; 电路信息控制单元，被配置为在数据处理之前存储几个电路信息项，并且在数据处理的第一周期中根据经由控制线接收的规则信号来输出多个电路信息项中的第一个; 处理元件，被配置为构成根据第一电路信息项的执行电路，以使用来自数据线的数据执行计算，并输出计算结果; 数据寄存器，用于存储所述计算结果，并用于在第二周期中输出所述计算结果; 以及用于存储规则信号并在第二周期中输出规则信号的控制寄存器。半导体还包括控制器，被配置为控制规则信号的输出定时到流水线中的计算单元的第一级的控制线，并且控制数据到第一级计算的数据线的输出定时单元，使得多个计算单元作为流水线操作。

36. 发明申请

US20050111354A1 Controlling bandwidth reservations method and apparatus 有权
标题翻译：控制带宽预留方法和装置
公开(公告)号：US20050111354A1
公开(公告)日：2005-05-26
申请号：US10718302
申请日：2003-11-20
申请人： Shigehiro Asano , Charles Johns , Matthew King , Peichun Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Johns , Matthew King , Peichun Liu , David Mui , Jieming Qi
IPC分类号： H04L12/24 , H04L12/26
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译：公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。任何非托管命令或数据包都按常规技术处理。

37. 发明授权

US6110547A Method of molding automobile outer trim part, laminated film or sheet for use therein and automobile outer trim part 失效
标题翻译：汽车外饰件，其中使用的层压膜或片材以及汽车外饰件的成型方法
公开(公告)号：US6110547A
公开(公告)日：2000-08-29
申请号：US53080
申请日：1998-04-01
申请人： Yutaka Sano , Shigehiro Asano , Satoshi Matsuura , Tsutomu Okano , Haruo Fukuda , Toshihiko Inagaki
发明人： Yutaka Sano , Shigehiro Asano , Satoshi Matsuura , Tsutomu Okano , Haruo Fukuda , Toshihiko Inagaki
IPC分类号： B29C45/00 , B29C45/14 , B29C45/16 , B29C51/00 , B29C69/02 , B29K23/00 , B29L9/00 , B29L31/30 , B32B27/32 , C08L23/16 , B60R13/00
CPC分类号： B32B27/32 , B29C45/14811 , B29C69/02 , B29C45/00 , B29C51/00 , B29K2995/002 , B29K2995/0026 , B29L2009/00 , B29L2031/302 , B29L2031/3041
摘要： Disclosed is a method of molding an automobile outer trim part, including the steps of: (1) providing a film or sheet comprising a colored layer composed of a propylene polymer composition and, laminated thereto, a clear layer composed of a propylene homopolymer, (a) heating the laminated film or sheet, (3) feeding the heated laminated film or sheet into a metal mold including a pair of dies, (4) closing the metal mold so that the laminated film or sheet is shaped into desired configuration, (5) loosing the closed metal mold, and (6) injecting a thermoplastic polymer onto the side of the colored layer of the metal mold so that the shaped laminated film or sheet is united with a substrate layer of the thermoplastic polymer. The above propylene polymer composition comprises in a specified proportion a polypropylene block copolymer and/or polypropylene random copolymer exhibiting a specified intrinsic viscosity, a polyethylene exhibiting a specified intrinsic viscosity, an elastomer composed of a copolymer of ethylene and an .alpha.-olefin exhibiting a specified intrinsic viscosity and a colorant. The above method enables providing an automobile outer trim part having the same colored appearance and texture as those of painted part, irrespective of the avoidance of a printing step.
摘要翻译：公开了一种模制汽车外饰件的方法，包括以下步骤：（1）提供包含由丙烯聚合物组合物构成的着色层的膜或片材，并且层叠有由丙烯均聚物构成的透明层（ a）加热层叠膜或片材，（3）将加热的层压膜或片材进给到包括一对模具的金属模具中，（4）关闭金属模具，使得层压膜或片材成形为所需的形状（ 5）松开封闭的金属模具，和（6）将热塑性聚合物注入到金属模具的着色层的一侧，使得成型的叠层膜或片与热塑性聚合物的基底层结合。上述丙烯聚合物组合物以规定比例包含显示特定特性粘度的聚丙烯嵌段共聚物和/或聚丙烯无规共聚物，显示特定特性粘度的聚乙烯，由乙烯和表现出特定粘度的α-烯烃的共聚物组成的弹性体特性粘度和着色剂。上述方法能够提供具有与涂漆部分相同的着色外观和质感的汽车外饰件，而不管避免印刷步骤。

38. 发明授权

US5572710A High speed logic simulation system using time division emulation suitable for large scale logic circuits 失效
标题翻译：高速逻辑仿真系统采用适合大规模逻辑电路的时分仿真
公开(公告)号：US5572710A
公开(公告)日：1996-11-05
申请号：US120220
申请日：1993-09-13
申请人： Shigehiro Asano , Shouzou Isobe , Jiro Amemiya , Hirofumi Muratani
发明人： Shigehiro Asano , Shouzou Isobe , Jiro Amemiya , Hirofumi Muratani
IPC分类号： G06F17/50 , G06F17/00 , G06F9/455
CPC分类号： G06F17/5027 , G06F17/5022 , Y10S706/92 , Y10S706/921
摘要： A logic simulation system capable of handling a very large scale circuit while realizing a high speed simulation by retaining the parallelism of the simulation targets. The system includes: a host computer having data of the simulation target divided into a plurality of sections defining different simulation phases to be executed sequentially in time division; an emulator for emulating the simulation target, including: a plurality of programmable emulation chips for mapping the simulation target, each emulation chip having a memory with a plurality of memory banks provided in correspondence to the plurality of sections for registering mapping data specifying a function to be realized by each emulation chip in emulating each of the plurality of sections; a programmable network for interconnecting the plurality of emulation chips; and an emulation control unit for controlling the plurality of emulation chips and the network by sequentially switching the memory banks of the memory of each emulation chip and changing connections among the plurality of emulation chips provided by the network in emulating each of the plurality of sections; and an interface unit for interfacing the host computer and the emulator.
摘要翻译：一种逻辑仿真系统，能够通过保持模拟目标的并行性实现高速仿真，处理大规模电路。该系统包括：具有模拟目标的数据的主计算机，被划分为定义不同模拟阶段的多个部分，以便按时间顺序执行; 用于仿真所述模拟目标的仿真器，包括：用于映射所述模拟目标的多个可编程仿真芯片，每个仿真芯片具有存储器，所述存储器具有与所述多个部分对应地设置的多个存储体，用于将指定功能的映射数据注册到每个仿真芯片在模拟多个部分中的每个部分时实现; 用于互连所述多个仿真芯片的可编程网络; 以及仿真控制单元，用于通过顺序地切换每个仿真芯片的存储器的存储器并且改变由所述网络提供的所述多个仿真芯片中的模拟所述多个部分中的每一个的连接，来控制所述多个仿真芯片和所述网络; 以及用于连接主计算机和仿真器的接口单元。

39. 发明授权

US08583972B2 Method of controlling a semiconductor storage device 有权
标题翻译：控制半导体存储装置的方法
公开(公告)号：US08583972B2
公开(公告)日：2013-11-12
申请号：US13486718
申请日：2012-06-01
申请人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
发明人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
IPC分类号： G11C29/00
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.
摘要翻译：一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定。该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。

40. 发明授权

US08402251B2 Selecting configuration memory address for execution circuit conditionally based on input address or computation result of preceding execution circuit as address 失效
标题翻译：根据前面执行电路的输入地址或计算结果作为地址，有条件地选择执行电路的配置存储器地址
公开(公告)号：US08402251B2
公开(公告)日：2013-03-19
申请号：US12544122
申请日：2009-08-19
申请人： Takashi Yoshikawa , Shigehiro Asano
发明人： Takashi Yoshikawa , Shigehiro Asano
IPC分类号： G06F9/38
CPC分类号： G06F15/7867
摘要： A semiconductor device includes a first circuit that executes a first calculation, a second circuit that includes a first storage unit therein and executes a second calculation, a controller that outputs a first address for specifying a first execution circuit for the first calculation and a second execution circuit for the second calculation, to the first circuit and the second circuit, and controls input of data into the first circuit, and a bus that transfers a result of the first calculation executed by the first circuit to the second circuit, wherein the result of the first calculation can be conditionally used as an address for specifying the second execution circuit.
摘要翻译：半导体器件包括执行第一计算的第一电路，包括第一存储单元并执行第二计算的第二电路，输出用于指定用于第一计算的第一执行电路的第一地址和第二执行的控制器用于第二次计算的电路，到第一电路和第二电路，并且控制数据到第一电路的输入以及将由第一电路执行的第一次计算的结果传送到第二电路的总线，其中，可以有条件地将第一计算用作用于指定第二执行电路的地址。

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