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31. 发明授权

US08174294B1 Configurable buffer circuits and methods 有权
标题翻译：可配置缓冲电路和方法
公开(公告)号：US08174294B1
公开(公告)日：2012-05-08
申请号：US12910177
申请日：2010-10-22
申请人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
发明人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
IPC分类号： H03B1/00
CPC分类号： H04L25/0272
摘要： A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circuit coupled to the first and the second resistors. The third switch circuit couples the first and the second resistors to a node at a first voltage when the buffer circuit is configured to function in a current mode logic buffer mode. The third switch circuit couples the first and the second resistors to a node at a second voltage when the buffer circuit is configured to function in an H-bridge buffer mode.
摘要翻译：缓冲电路包括电流源电路，耦合到电流源电路的第一和第二开关电路，耦合到第一开关电路的第一电阻器，耦合到第二开关电路的第二电阻器和耦合到第二开关电路的第三开关电路，第一和第二电阻。当缓冲电路被配置为以当前模式逻辑缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第一电压的节点。当缓冲电路被配置为以H桥缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第二电压的节点。

32. 发明授权

US08744012B1 On-chip eye viewer architecture for highspeed transceivers 有权
标题翻译：用于高速收发器的片上眼睛查看器架构
公开(公告)号：US08744012B1
公开(公告)日：2014-06-03
申请号：US13369108
申请日：2012-02-08
申请人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
IPC分类号： H03K9/00
CPC分类号： H04L1/203 , G01R31/31711
摘要： System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.
摘要翻译：提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

33. 发明授权

US08504882B2 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations 有权
标题翻译：用于执行或促进示波器，抖动和/或误码率测试仪操作的集成电路的电路
公开(公告)号：US08504882B2
公开(公告)日：2013-08-06
申请号：US12884305
申请日：2010-09-17
申请人： Peng Li , Masashi Shimanouchi , Sergey Shumarayev , Weiqi Ding , Siriram Narayan , Daniel Tun Lai Chow , Mingde Pan
发明人： Peng Li , Masashi Shimanouchi , Sergey Shumarayev , Weiqi Ding , Siriram Narayan , Daniel Tun Lai Chow , Mingde Pan
IPC分类号： G06F11/00
CPC分类号： G06F11/267
摘要： An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.
摘要翻译：集成电路（“IC”）包括用于测试串行数据信号的电路。一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。这样的IC提供指示其操作结果的输出信号。一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

34. 发明申请

US20120072785A1 BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER 有权
标题翻译：从眼睛观察器接收串行数据信号的位错误率检查器
公开(公告)号：US20120072785A1
公开(公告)日：2012-03-22
申请号：US12884923
申请日：2010-09-17
申请人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
发明人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
IPC分类号： G06F11/00
CPC分类号： H04L1/203 , G01R31/3171
摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.
摘要翻译：提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。在一个实现中，BER检查器是专用的BER检查器。在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

35. 发明申请

US20120072784A1 CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS 有权
标题翻译：用于执行或促进OSCILLOSCOPE，JITTER和/或BIT错误率测试仪操作的集成电路的电路
公开(公告)号：US20120072784A1
公开(公告)日：2012-03-22
申请号：US12884305
申请日：2010-09-17
申请人： Peng Li , Masashi Shimanouchi , Sergey Shumarayev , Weiqi Ding , Sriram Narayan , Daniel Tun Lai Chow , Mingde Pan
发明人： Peng Li , Masashi Shimanouchi , Sergey Shumarayev , Weiqi Ding , Sriram Narayan , Daniel Tun Lai Chow , Mingde Pan
IPC分类号： G06F11/00
CPC分类号： G06F11/267
摘要： An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.
摘要翻译：集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等功能，用于在抖动容限，噪声容限等方面测试信号和电路。

36. 发明授权

US09429625B1 Analog signal test circuits and methods 有权
标题翻译：模拟信号测试电路及方法
公开(公告)号：US09429625B1
公开(公告)日：2016-08-30
申请号：US13475256
申请日：2012-05-18
申请人： Weiqi Ding , Sergey Shumarayev
发明人： Weiqi Ding , Sergey Shumarayev
IPC分类号： G01R31/00 , G01R31/319 , G01R31/40
CPC分类号： G01R31/31924 , G01R31/3167 , G01R31/40
摘要： An analog test network includes a conductor. The conductor is coupled to provide a first analog signal from a circuit under test to an analog-to-digital converter circuit. The analog-to-digital converter circuit is operable to generate a first digital signal based on the first analog signal. A control circuit is operable to generate a second digital signal based on the first digital signal. A digital-to-analog converter circuit is operable to generate a second analog signal based on the second digital signal. The conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the circuit under test.
摘要翻译：模拟测试网络包括导体。导体被耦合以从被测电路提供到模拟 - 数字转换器电路的第一模拟信号。模数转换器电路可操作以基于第一模拟信号产生第一数字信号。控制电路可操作以基于第一数字信号产生第二数字信号。数模转换器电路可操作以基于第二数字信号产生第二模拟信号。导体被耦合以将第二模拟信号从数模转换器电路提供给被测电路。

37. 发明授权

US08723572B1 Apparatus and methods to correct differential skew and/or duty cycle distortion 有权
标题翻译：校正差分偏移和/或占空比失真的装置和方法
公开(公告)号：US08723572B1
公开(公告)日：2014-05-13
申请号：US13436385
申请日：2012-03-30
申请人： Weiqi Ding , Sergey Shumarayev
发明人： Weiqi Ding , Sergey Shumarayev
IPC分类号： H03K5/12
CPC分类号： H03K5/1565
摘要： One embodiment relates a method of correcting skew and/or duty cycle distortion in a differential signal using a transmitter buffer circuit. Skew and/or duty cycle distortion may be detected in the differential signal. Delay times for at least two variable-delay buffer circuits are adjusted. The variable-delay buffer circuits may have outputs coupled to control gates of pull-up and pull-down transistors coupled to one or more output nodes of the transmitter buffer circuit. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及使用发射机缓冲电路来校正差分信号中的偏移和/或占空比失真的方法。可以在差分信号中检测到偏斜和/或占空比失真。调整至少两个可变延迟缓冲电路的延迟时间。可变延迟缓冲电路可以具有耦合到耦合到发送器缓冲电路的一个或多个输出节点的上拉和下拉晶体管的控制栅极的输出。还公开了其它实施例，方面和特征。

38. 发明授权

US09222972B1 On-die jitter generator 有权
标题翻译：裸片抖动发生器
公开(公告)号：US09222972B1
公开(公告)日：2015-12-29
申请号：US12884747
申请日：2010-09-17
申请人： Weiqi Ding , Sergey Shumarayev , Mingde Pan , Peng Li , Masashi Shimanouchi
发明人： Weiqi Ding , Sergey Shumarayev , Mingde Pan , Peng Li , Masashi Shimanouchi
IPC分类号： G01R31/02 , G01R31/317
CPC分类号： G01R31/31709
摘要： An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.
摘要翻译：提供了包括抖动发生器的IC，其中抖动发生器与IC集成并产生非固有抖动。在一个实现中，非固有抖动用于测量IC的特性。在一个实现中，非固有抖动用于测试IC的抖动容限。在又一实现中，使用非固有抖动来测试耦合到包括抖动发生器的IC的另一IC。

39. 发明授权

US08395421B1 Configurable buffer circuits and methods 有权
标题翻译：可配置缓冲电路和方法
公开(公告)号：US08395421B1
公开(公告)日：2013-03-12
申请号：US13446772
申请日：2012-04-13
申请人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
发明人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
IPC分类号： H03B1/00
CPC分类号： H04L25/0272
摘要： A buffer circuit includes first and second inputs and first and second outputs. The buffer circuit is configurable to buffer a differential input signal received at the first and the second inputs to generate a differential output signal at the first and the second outputs in a current mode logic buffer mode based on a control signal. The buffer circuit is configurable to buffer the differential input signal to generate the differential output signal in an H-bridge buffer mode based on the control signal.
摘要翻译：缓冲电路包括第一和第二输入以及第一和第二输出。缓冲电路可配置为缓冲在第一和第二输入处接收的差分输入信号，以在基于控制信号的当前模式逻辑缓冲器模式中在第一和第二输出处产生差分输出信号。缓冲电路可配置为基于控制信号缓冲差分输入信号以产生H桥缓冲器模式中的差分输出信号。

40. 发明授权

US08933751B1 High resolution capacitor 有权
标题翻译：高分辨率电容
公开(公告)号：US08933751B1
公开(公告)日：2015-01-13
申请号：US13475678
申请日：2012-05-18
申请人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
发明人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
IPC分类号： H03F3/45 , H01G4/40 , H03F1/56
CPC分类号： H01G4/40 , H01G17/00 , H03F1/56
摘要： A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.
摘要翻译：具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。每个开关电容器包括开关电容器和串联耦合的开关。在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。

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