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31. 发明申请

US20060208361A1 Semiconductor chip 失效
标题翻译：半导体芯片
公开(公告)号：US20060208361A1
公开(公告)日：2006-09-21
申请号：US11368671
申请日：2006-03-07
申请人： Koichi Ohto , Tatsuya Usami
发明人： Koichi Ohto , Tatsuya Usami
IPC分类号： H01L23/52
CPC分类号： H01L23/5329 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/31633 , H01L21/78 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip 100 includes a semiconductor substrate (not shown), and a stacked film 150 formed over the semiconductor substrate, which includes carbon-containing insulating films such as a first interlayer insulating film 106, and carbon-free insulating films such as an underlying layer 102 and a top cover film 124. The end faces of the carbon-free insulating films herein are located on the outer side of the end faces of the carbon-containing insulating films. The carbon composition of the carbon-containing insulating films is lowered in the end portions thereof than in the inner portions. The film density of the carbon-containing insulating films is raised in the end portions thereof than in the inner portions.
摘要翻译：半导体芯片100包括半导体衬底（未示出）和形成在半导体衬底上的叠层膜150，其包括含碳绝缘膜如第一层间绝缘膜106和无碳绝缘膜，例如底层层102和顶盖膜124。这里的无碳绝缘膜的端面位于含碳绝缘膜的端面的外侧。含碳绝缘膜的碳组成在其端部比在内部降低。含碳绝缘膜的膜密度在其端部比在内部部分高。

32. 发明申请

US20060186549A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060186549A1
公开(公告)日：2006-08-24
申请号：US11355003
申请日：2006-02-16
申请人： Tatsuya Usami , Koichi Ohto , Toshiyuki Takewaki
发明人： Tatsuya Usami , Koichi Ohto , Toshiyuki Takewaki
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76867 , H01L21/02203 , H01L21/02329 , H01L21/3143 , H01L21/76826 , H01L21/76829 , H01L21/76849 , H01L21/76886
摘要： A first gas including a silicon-containing compound is introduced into a vacuum chamber, to expose a semiconductor substrate placed in the chamber to the first gas atmosphere (silicon processing step). Then the pressure inside the vacuum chamber is reduced to a level lower than the pressure at the time of starting the silicon processing step (depressurizing step). Thereafter, a second gas including a nitrogen-containing compound is introduced into the vacuum chamber, and the semiconductor substrate is irradiated with the second gas plasma (nitrogen plasma step).
摘要翻译：将包含含硅化合物的第一气体引入真空室中，以将放置在室内的半导体衬底暴露于第一气体气氛（硅处理步骤）。然后将真空室内的压力降低到低于开始硅处理步骤（减压步骤）时的压力的水平。此后，将包含含氮化合物的第二气体引入真空室中，并用第二气体等离子体（氮等离子体步骤）照射半导体衬底。

33. 发明授权

US07057286B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US07057286B2
公开(公告)日：2006-06-06
申请号：US10260947
申请日：2002-09-30
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L23/28
CPC分类号： H01L21/76835 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76832 , H01L2221/1036
摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

34. 发明授权

US07045898B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US07045898B2
公开(公告)日：2006-05-16
申请号：US10438887
申请日：2003-05-16
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/7684 , H01L21/76849
摘要： There is presented a structure in which outlines of a metal interconnection 111 that is laid in an interlayer insulating film are covered with a barrier metal film 110. As the material for the barrier metal film 110, TaN or the like is utilized.

35. 发明申请

US20060060975A1 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060060975A1
公开(公告)日：2006-03-23
申请号：US11219784
申请日：2005-09-07
申请人： Tatsuya Usami , Noboru Morita , Koichi Ohto
发明人： Tatsuya Usami , Noboru Morita , Koichi Ohto
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76834 , H01L21/76804 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device comprises a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device comprises an electric conductor, which is provided to extend through the multiple-layered insulating film 140 and includes a Cu film 120 and a barrier metal film 118. The barrier metal film 118 is provided so as to cover side surfaces and a bottom surface of the Cu film 120. This semiconductor device comprises an insulating film 116, which is disposed between the multiple-layered insulating film 140 and the electric conductor (i.e., Cu film 120 and barrier metal film 118).
摘要翻译：提供了一种用于抑制在半导体器件中发生的绝缘击穿的技术。半导体器件包括半导体衬底（未示出），形成在半导体衬底上的层间绝缘膜102和设置在层间绝缘膜102上的多层绝缘膜140。半导体器件包括导电体，其设置成延伸穿过多层绝缘膜140并且包括Cu膜120和阻挡金属膜118。阻挡金属膜118被设置为覆盖Cu膜120的侧表面和底表面。该半导体器件包括设置在多层绝缘膜140和导电体（即Cu膜120和阻挡金属膜118）之间的绝缘膜116。

36. 发明申请

US20050179137A1 Semiconductor device having copper damascene interconnection and fabricating method thereof 审中-公开
标题翻译：具有铜镶嵌互连的半导体装置及其制造方法
公开(公告)号：US20050179137A1
公开(公告)日：2005-08-18
申请号：US11101416
申请日：2005-04-08
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L23/532 , H01L23/52
CPC分类号： H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A silicon carbon nitride film is formed on an interlayer dielectric film having Si—H bonds and a Cu interconnection. The silicon carbon nitride film has the role of blocking moisture absorption and prevents deterioration associated with the moisture absorption by a lower-layer insulating film and a Cu film, thereby suppressing an increase in the capacitance between interconnections or via resistance. The effect is great especially when the nitrogen concentration of the silicon carbon nitride film is not less than 10 atm % but less than 35 atm %. Between the interlayer dielectric film having Si—H bonds and the Cu interconnection is interposed a laminated film of a Ta film and a TaN film as a barrier metal film in such a manner that the TaN film becomes on the side of the interlayer dielectric film.
摘要翻译：在具有Si-H键和Cu互连的层间电介质膜上形成碳氮化硅膜。硅氮化硅膜具有阻止吸湿的作用，并且防止与下层绝缘膜和Cu膜的吸湿相关的劣化，从而抑制互连或通孔电阻之间的电容的增加。特别是当氮化硅氮化物膜的氮浓度不小于10atm％但小于35atm％时，效果非常好。在具有Si-H键的层间电介质膜和Cu互连之间插入有Ta膜和TaN膜的叠层膜作为阻挡金属膜，使得TaN膜成为层间电介质膜的一侧。

37. 发明授权

US06930036B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06930036B2
公开(公告)日：2005-08-16
申请号：US10695159
申请日：2003-10-28
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L21/311 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/76835 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76832 , H01L2221/1036
摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.
摘要翻译：在半导体器件中制造多电平互连结构的方法包括在第一层Cu层上连续形成抗扩散膜和层间电介质膜的步骤，在层间绝缘膜上形成第一至第三硬掩模膜，通过使用第一硬掩模来形成第一硬掩模以蚀刻层间电介质膜，通过使用第三硬掩模膜来蚀刻第一和第二硬掩模膜和层间绝缘膜的顶部以形成沟槽，扩散膜形成通孔。第一硬掩模膜在去除第二和第三硬掩模膜期间保护层间电介质膜。

38. 发明授权

US06670709B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06670709B2
公开(公告)日：2003-12-30
申请号：US09779584
申请日：2001-02-09
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L23485
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807 , H01L21/76825 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A first HSQ film composed of a Si—O-based film with a low dielectric constant is formed on a first wiring via a protective insulation film, and the surface of this first HSQ film is reformed to form a first SRO layer. Then, a second HSQ film is formed on this first SRO layer, and the surface of the second HSQ film is reformed to form a second SRO layer. Next, a via-hole is formed within a predetermined region, which reaches the protective insulation film on the first wiring. Then, wiring trenches forming a second wiring are formed within predetermined regions of the second HSQ film and the second SRO film while using the first SRO film as an etching stopper film. Thereafter, the protective insulation film at the bottom of the via-hole is etched and removed, and the wiring trenches and the via-hole are embedded with a conductive film. Then, the conductive film on the second SRO layer is removed while using the second SRO layer as a CMP stopper film.
摘要翻译：通过保护绝缘膜在第一布线上形成由具有低介电常数的Si-O基膜构成的第一HSQ膜，并将该第一HSQ膜的表面重整形成第一SRO层。然后，在该第一SRO层上形成第二HSQ膜，将第二HSQ膜的表面重新形成第二SRO层。接下来，在到达第一布线上的保护绝缘膜的预定区域内形成通孔。然后，在使用第一SRO膜作为蚀刻停止膜的同时，在第二HSQ膜和第二SRO膜的预定区域内形成形成第二布线的布线沟槽。此后，蚀刻去除通孔底部的保护绝缘膜，并且布线沟槽和通孔嵌入导电膜。然后，在使用第二SRO层作为CMP阻挡膜的同时去除第二SRO层上的导电膜。

39. 发明授权

US06514852B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06514852B2
公开(公告)日：2003-02-04
申请号：US09910994
申请日：2001-07-23
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76832 , H01L2221/1036
摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

40. 发明授权

US06383927B2 Process for fabricating semiconductor device, apparatus using more than one kind of inert gas for evacuating air and method for entering wafer into the apparatus 失效
标题翻译：用于制造半导体器件的方法，使用一种以上惰性气体排空空气的装置以及将晶片输入设备的方法
公开(公告)号：US06383927B2
公开(公告)日：2002-05-07
申请号：US09513926
申请日：2000-02-28
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , H01L21/02134 , H01L21/02238 , H01L21/02255 , H01L21/02282 , H01L21/28211 , H01L21/31058 , H01L21/3124 , H01L21/31662 , H01L21/324 , Y10S438/913
摘要： Semiconductor wafers on a boat are inserted into a furnace chamber of a vertical oxidation/diffusion furnace, and helium gas and argon gas are injected into the furnace chamber during the insertion of the boat, so that the light helium gas fills the furnace chamber without residual air and the heavy argon gas pushes out the residual air from gaps between the semiconductor wafers.
摘要翻译：将船上的半导体晶片插入垂直氧化/扩散炉的炉室中，并且在船的插入期间将氦气和氩气注入炉室中，使得轻氦气填充炉室而不残留空气和重氩气从半导体晶片之间的间隙推出剩余空气。

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