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31. 发明授权

US07606955B1 Single wire bus for connecting devices and methods of operating the same 有权
标题翻译：用于连接设备的单线总线及其操作方法
公开(公告)号：US07606955B1
公开(公告)日：2009-10-20
申请号：US10931933
申请日：2004-09-01
申请人： Ohad Falik , Victor Flachs
发明人： Ohad Falik , Victor Flachs
IPC分类号： G06F13/00 , G06F3/00 , G06F5/00 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4295
摘要： A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective bus interfaces coupled to the bus. Each of the slave devices having a designated device identification. There is further provided a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions composed each of bit signals that belong each to a bit signal type from among a plurality of bit signal types. Each bit signal type has a time interval that is discernible from respective time intervals of all other bit signal types from among the plurality of bit signal types.
摘要翻译：主/从系统架构，其包括单线总线，主设备和耦合到总线的总线接口。该系统还包括具有耦合到总线的相应总线接口的多个从设备。每个从设备具有指定的设备标识。还提供了通过单线总线实现并由主设备和从设备采用的通信协议。该协议包括由多个比特信号类型中的每一个位信号组合成位信号类型的总线事务。每个比特信号类型具有从多个比特信号类型中的所有其他比特信号类型的各个时间间隔可以看出的时间间隔。

32. 发明授权

US07562283B2 Systems and methods for error correction using binary coded hexidecimal or hamming decoding 失效
标题翻译：使用二进制编码十六进制或汉明译码进行纠错的系统和方法
公开(公告)号：US07562283B2
公开(公告)日：2009-07-14
申请号：US11325677
申请日：2006-01-05
申请人： Ohad Falik , Yuval Itkin
发明人： Ohad Falik , Yuval Itkin
IPC分类号： H03M13/00
CPC分类号： G06F11/1012 , H03M13/152 , H03M13/159 , H03M13/19 , H03M13/2906
摘要： Systems and methods for error correction of data. In one embodiment of the invention, a plurality of error correction schemes are applied when encoding data and depending on the circumstances, one or more of those schemes is selected to decode the data. In one of these embodiments, the applied error correction schemes include the BCH algorithm and the Hamming algorithm.
摘要翻译：用于数据纠错的系统和方法。在本发明的一个实施例中，在编码数据时应用多个纠错方案，并且根据情况，选择这些方案中的一个或多个来解码数据。在这些实施例中的一个中，应用的纠错方案包括BCH算法和汉明算法。

33. 发明申请

US20080301398A1 LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES 有权
标题翻译：线性到物理地址翻译，支持页面属性
公开(公告)号：US20080301398A1
公开(公告)日：2008-12-04
申请号：US11757103
申请日：2007-06-01
申请人： Ohad Falik , Ben-Zion Friedman , Jack Doweck , Eliezer Weissmann , James B. Crossland
发明人： Ohad Falik , Ben-Zion Friedman , Jack Doweck , Eliezer Weissmann , James B. Crossland
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。系统可以返回物理内存地址和一个或多个页面属性。描述和要求保护其他实施例。

34. 发明申请

US20080195791A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 有权
公开(公告)号：US20080195791A1
公开(公告)日：2008-08-14
申请号：US11933159
申请日：2007-10-31
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dian Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dian Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/36
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

35. 发明授权

US07318173B1 Embedded controller based BIOS boot ROM select 有权
标题翻译：基于嵌入式控制器的BIOS启动ROM选择
公开(公告)号：US07318173B1
公开(公告)日：2008-01-08
申请号：US10453851
申请日：2003-06-03
申请人： Ohad Falik , Ilia Stolov
发明人： Ohad Falik , Ilia Stolov
IPC分类号： G06F11/00
CPC分类号： G06F11/1433 , G06F9/4401 , G06F9/441
摘要： A method for selecting one of a plurality of BIOS images included in a computer system includes indicating a selection of a BIOS image via a bus by an embedded controller. The method also includes powering up or resetting the system. In addition, the method includes accessing the selected BIOS image for execution.
摘要翻译：一种用于选择包括在计算机系统中的多个BIOS映像之一的方法包括：通过嵌入式控制器通过总线指示BIOS图像的选择。该方法还包括上电或复位系统。此外，该方法包括访问所选择的BIOS映像以供执行。

36. 发明授权

US06173355B2 System for sending and receiving data on a universal serial bus (USB) using a memory shared among a number of endpoints 有权
标题翻译：在通用串行总线（USB）上使用多个端点共享的存储器发送和接收数据的系统
公开(公告)号：US06173355B2
公开(公告)日：2001-01-09
申请号：US09469663
申请日：1999-12-22
申请人： Ohad Falik , David Brief
发明人： Ohad Falik , David Brief
IPC分类号： G06F1314
CPC分类号： G06F13/4295 , H04L1/1835 , H04L1/1848 , H04L49/90 , H04L49/901 , H04L2001/0094
摘要： An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of end points are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission retry.
摘要翻译：公开了一种使用在多个端点之间共享的存储器在通用串行总线上发送和接收数据的方法的装置。存储器是双缓冲器，其允许在当前分组被发送时准备下一个分组。本发明还支持传输重试。

37. 发明授权

US09311145B2 Using platform idle duration information to notify platform devices of upcoming active periods 有权
标题翻译：使用平台空闲持续时间信息通知平台设备即将到来的活动期间
公开(公告)号：US09311145B2
公开(公告)日：2016-04-12
申请号：US13719898
申请日：2012-12-19
申请人： Christian Maciocco , Ohad Falik , Ren Wang , Tsung-Yuan C. Tai
发明人： Christian Maciocco , Ohad Falik , Ren Wang , Tsung-Yuan C. Tai
IPC分类号： G06F3/00 , G06F9/48 , G06F9/54 , G06F1/32
CPC分类号： G06F9/4893 , G06F1/3206 , G06F9/54 , Y02D10/24
摘要： Methods and systems may provide for determining a next active window for a platform and notifying one or more of a plurality of devices of the platform of the next active window being determined. Additionally, one or more of the plurality of devices may be notified of an onset of the next active window. In one example, a pre-warm message is issued to notify one or more of the plurality of devices of the next active window being determined.
摘要翻译：方法和系统可以提供用于确定平台的下一个活动窗口并通知所确定的下一活动窗口的平台的多个设备中的一个或多个设备。另外，可以向多个设备中的一个或多个通知下一活动窗口的开始。在一个示例中，发出预热消息以通知所确定的下一个活动窗口的多个设备中的一个或多个。

38. 发明授权

US09152205B2 Mechanism for facilitating faster suspend/resume operations in computing systems 有权
标题翻译：促进计算系统中更快的挂起/恢复操作的机制
公开(公告)号：US09152205B2
公开(公告)日：2015-10-06
申请号：US13596915
申请日：2012-08-28
申请人： Ohad Falik , Eliezer Weissmann , Alon Naveh , Michael Mishaeli , Nadav Shulman , Robert E. Gough , Erik C. Bjorge , Douglas R. Moran , Peter A. Dice
发明人： Ohad Falik , Eliezer Weissmann , Alon Naveh , Michael Mishaeli , Nadav Shulman , Robert E. Gough , Erik C. Bjorge , Douglas R. Moran , Peter A. Dice
IPC分类号： G06F1/32 , G06F9/44
CPC分类号： G06F1/3206 , G06F9/4418
摘要： A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.
摘要翻译：描述了根据本发明的一个实施例的用于促进计算系统中更快的挂起/恢复操作的机制。本发明的实施例的方法包括：响应于在计算系统处的睡眠呼叫，将入口处理发起到第一睡眠状态，从第一休眠状态转换到第二休眠状态。转换可以包括在与计算系统处理器的一个或多个处理器核心相关联的本地存储器处保留处理器上下文的至少一部分。该方法还可以包括进入第二睡眠状态。

39. 发明授权

US09015510B2 Optimizing energy efficiency using device idle duration information and latency tolerance based on a pre-wake configuration of a platform associated to the device 有权
标题翻译：基于与设备相关联的平台的前唤醒配置，使用设备空闲持续时间信息和延迟容限优化能量效率
公开(公告)号：US09015510B2
公开(公告)日：2015-04-21
申请号：US13537260
申请日：2012-06-29
申请人： Christian Maciocco , Ohad Falik , Ren Wang , Nadav Shulman , Paul Diefenbaugh , Tsung-Yuan Charles Tai
发明人： Christian Maciocco , Ohad Falik , Ren Wang , Nadav Shulman , Paul Diefenbaugh , Tsung-Yuan Charles Tai
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3228
摘要： Systems and methods may provide for aggregating a first idle duration from a first device associated with a platform and a second idle duration from a second device associated with the platform. Additionally, an idle state may be selected for the platform based at least in part on the first idle duration and the second idle duration. In one example, the idle durations are classified as deterministic, estimated or statistical.
摘要翻译：系统和方法可以提供从与平台相关联的第一设备和与平台相关联的第二设备的第二空闲持续时间聚集第一空闲持续时间。另外，可以至少部分地基于第一空闲持续时间和第二空闲持续时间来为平台选择空闲状态。在一个示例中，空闲持续时间被分类为确定性，估计或统计。

40. 发明申请

US20130346728A1 Optimizing Performance Of Instructions Based On Sequence Detection Or Information Associated With The Instructions 有权
标题翻译：基于序列检测或与指令相关的信息优化指令性能
公开(公告)号：US20130346728A1
公开(公告)日：2013-12-26
申请号：US14012344
申请日：2013-08-28
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。描述和要求保护其他实施例。

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