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31. 发明授权

US07721165B2 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US07721165B2
公开(公告)日：2010-05-18
申请号：US11599388
申请日：2006-11-15
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

32. 发明授权

US07715243B2 Storage device employing a flash memory 失效
标题翻译：采用闪存的存储设备
公开(公告)号：US07715243B2
公开(公告)日：2010-05-11
申请号：US12000696
申请日：2007-12-17
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G11C7/10
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2003/0694 , G06F2212/2022 , G11C16/102 , G11C16/349
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.
摘要翻译：采用其中以块为单位重写数据的闪存的半导体盘作为存储介质，该半导体盘包括存储有文件数据的数据存储器，代替数据存储器中的错误块的替换存储器，存储有数据存储器的错误信息的错误存储器，以及从数据存储器，替代存储器和错误存储器读取数据并将数据写入数据存储器，替代存储器和错误存储器的数据的存储器控制器。由于可以补救闪速存储器的写入错误，所以可以提高半导体盘的使用寿命。

33. 发明授权

US07694067B2 Memory card 有权
标题翻译：存储卡
公开(公告)号：US07694067B2
公开(公告)日：2010-04-06
申请号：US12015050
申请日：2008-01-16
申请人： Nagamasa Mizushima , Takashi Tsunehiro , Motoyasu Tsunoda , Toshio Tanaka , Kunihiro Katayama , Koichi Kimura , Tomihisa Hatano
发明人： Nagamasa Mizushima , Takashi Tsunehiro , Motoyasu Tsunoda , Toshio Tanaka , Kunihiro Katayama , Koichi Kimura , Tomihisa Hatano
IPC分类号： G06F12/00
CPC分类号： G06K7/0021 , G06F21/602 , G06K7/0047 , G06K19/07732
摘要： A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
摘要翻译：提供了一种存储装置，其连接用于从主机装置提供的电源和时钟进行操作。存储器件包括外部端子，存储数据的闪存芯片，处理数据的IC芯片; 以及与外部端子，闪存芯片和IC芯片连接的控制器芯片。闪存芯片，IC芯片和控制器芯片是分立芯片。控制器芯片根据主机装置的命令将从主机装置输入的数据写入闪存芯片或IC芯片，并将从闪存芯片或IC芯片读取的数据传送到主机装置。

34. 发明授权

US07549086B2 Memory card and its initial setting method 有权
标题翻译：存储卡及其初始设定方法
公开(公告)号：US07549086B2
公开(公告)日：2009-06-16
申请号：US11877500
申请日：2007-10-23
申请人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

35. 发明申请

US20090013125A1 MEMORY CARD 有权
标题翻译：存储卡
公开(公告)号：US20090013125A1
公开(公告)日：2009-01-08
申请号：US12015050
申请日：2008-01-16
申请人： Nagamasa MIZUSHIMA , Takashi Tsunehiro , Motoyasu Tsunoda , Toshio Tanaka , Kunihiro Katayama , Koichi Kimura , Tomihisa Hatano
发明人： Nagamasa MIZUSHIMA , Takashi Tsunehiro , Motoyasu Tsunoda , Toshio Tanaka , Kunihiro Katayama , Koichi Kimura , Tomihisa Hatano
IPC分类号： G06F12/02
CPC分类号： G06K7/0021 , G06F21/602 , G06K7/0047 , G06K19/07732
摘要： A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
摘要翻译：提供了一种存储装置，其连接用于从主机装置提供的电源和时钟进行操作。存储器件包括外部端子，存储数据的闪存芯片，处理数据的IC芯片; 以及与外部端子，闪存芯片和IC芯片连接的控制器芯片。闪存芯片，IC芯片和控制器芯片是分立芯片。控制器芯片根据主机装置的命令将从主机装置输入的数据写入闪存芯片或IC芯片，并将从闪存芯片或IC芯片读取的数据传送到主机装置。

36. 发明授权

US07343445B2 Non-volatile memory card and transfer interruption means 有权
标题翻译：非易失性存储卡和传输中断手段
公开(公告)号：US07343445B2
公开(公告)日：2008-03-11
申请号：US11541543
申请日：2006-10-03
申请人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
发明人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译：存储卡设置有传送控制电路，写入控制电路和判断电路。传送控制电路在数据传送期间输出传送标志信号。写入控制电路在数据写入操作期间输出内部忙信号。当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。

37. 发明授权

US07305589B2 Memory card and its initial setting method 有权
标题翻译：存储卡及其初始设定方法
公开(公告)号：US07305589B2
公开(公告)日：2007-12-04
申请号：US10484043
申请日：2002-05-08
申请人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，该数据FD与先前存储在ROM中的操作检查数据FD1＆lt; 1＆gt; 存储在ROM4a中的写入检查数据FD1＆lt; 2＆gt;如果没有检测到故障则被写入闪速存储器2，并且再次读取该数据并与写入检查进行比较 ROM4a的数据FD1 <2> 。当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在数据比较中检测到故障，则CPU将复位过程故障数据设置为寄存器5a以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

38. 发明申请

US20070253251A1 IC MODULE AND CELLULAR PHONE 失效
标题翻译： IC模块和蜂窝电话
公开(公告)号：US20070253251A1
公开(公告)日：2007-11-01
申请号：US11740961
申请日：2007-04-27
申请人： Nagamasa Mizushima , Kunihiro Katayama , Masaharu Ukeda , Yoshinori Mochizuki
发明人： Nagamasa Mizushima , Kunihiro Katayama , Masaharu Ukeda , Yoshinori Mochizuki
IPC分类号： G11C16/04
CPC分类号： G06K19/0723 , G06K19/07 , G06K19/072 , G06Q20/105
摘要： In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to the flash memory chip) using power supplied from the host equipment to the contact IC card interface, and executes initialization of the flash memory chip between activation of the host equipment and completion of user authentication instructed by the host equipment.
摘要翻译：在具有闪速存储器芯片，存储器控制器芯片和接触/非接触卡接口的SIM卡中，存储器控制器芯片具有执行主机设备的用户认证的功能，执行通过非接触IC卡接口传输的数据的处理（使用从主机设备向接触式IC卡接口提供的电力执行对闪存芯片的数据读取或写入，并且在主机设备激活和主机设备指示的用户认证完成之间执行闪存芯片的初始化。

39. 发明申请

US20070070694A1 Storage device employing a flash memory 失效
公开(公告)号：US20070070694A1
公开(公告)日：2007-03-29
申请号：US11599308
申请日：2006-11-15
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G11C14/00
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2003/0694 , G06F2212/2022 , G11C16/102 , G11C16/349
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

40. 发明授权

US07133961B2 Non-volatile memory card and transfer interruption means 有权
标题翻译：非易失性存储卡和传输中断手段
公开(公告)号：US07133961B2
公开(公告)日：2006-11-07
申请号：US10195400
申请日：2002-07-16
申请人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
发明人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译：存储卡设置有传送控制电路，写入控制电路和判断电路。传送控制电路在数据传送期间输出传送标志信号。写入控制电路在数据写入操作期间输出内部忙信号。当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。

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