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31. 发明申请

US20160028395A1 ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK SYSTEM 有权
标题翻译：在多个RANK系统中没有专用PIN的终端控制
公开(公告)号：US20160028395A1
公开(公告)日：2016-01-28
申请号：US14498794
申请日：2014-09-26
申请人： Kuljit S. Bains , Nadav Bonen
发明人： Kuljit S. Bains , Nadav Bonen
IPC分类号： H03K19/00
CPC分类号： H03K19/0005 , G06F3/0604 , G06F3/061 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F13/4086 , H03K19/0008 , H03K19/017545 , H03K19/01825 , H03K19/018557
摘要： A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.
摘要翻译：存储器子系统包括多器件封装，其包括被组织为多级存储器的多个存储器件。用于存储器子系统的控制单元向存储器的一些或全部行同时发送存储器访问命令，并且触发接收存储器访问命令的所有存储器等级的一部分以改变管芯终端（ODT）设置。选择其中一个行执行存储器访问命令，并且在所有等级触发以改变ODT设置的情况下执行命令具有改变的ODT设置。

32. 发明授权

US09030903B2 Method, apparatus and system for providing a memory refresh 有权
标题翻译：用于提供存储器刷新的方法，装置和系统
公开(公告)号：US09030903B2
公开(公告)日：2015-05-12
申请号：US13625741
申请日：2012-09-24
申请人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
IPC分类号： G11C11/406 , G11C16/00 , G06F13/16
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译：一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。

33. 发明授权

US09009362B2 Variable-width command/address bus 有权
标题翻译：可变宽度命令/地址总线
公开(公告)号：US09009362B2
公开(公告)日：2015-04-14
申请号：US13722666
申请日：2012-12-20
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： G06F3/00 , G11C7/10 , G06F13/16
CPC分类号： G11C7/10 , G06F13/1668 , G06F13/1678 , G11C7/1045 , G11C2207/105 , G11C2207/108
摘要： Embodiments of the invention relate to a variable-width command/address bus (CA bus). In one embodiment, a memory controller includes first logic to determine whether a memory device is in a first mode or a second mode. The memory controller includes second logic to transmit a command to the memory device with a command/address bus having a first width over a first number of clock edges when the memory device is in the first mode, and with the command/address bus having a second width over a second number of clock edges when the memory device is in the second mode.
摘要翻译：本发明的实施例涉及可变宽度命令/地址总线（CA总线）。在一个实施例中，存储器控制器包括用于确定存储器件是处于第一模式还是第二模式的第一逻辑。存储器控制器包括第二逻辑，用于当存储器件处于第一模式时，具有在第一数量的时钟沿上具有第一宽度的命令/地址总线来向存储器件发送命令，并且命令/地址总线具有当存储器件处于第二模式时，在第二数量的时钟边缘上的第二宽度。

34. 发明申请

US20150067437A1 APPARATUS, METHOD AND SYSTEM FOR REPORTING DYNAMIC RANDOM ACCESS MEMORY ERROR INFORMATION 审中-公开
标题翻译：用于报告动态随机存取存储器错误信息的装置，方法和系统
公开(公告)号：US20150067437A1
公开(公告)日：2015-03-05
申请号：US14133288
申请日：2013-12-18
申请人： Kuljit S. Bains , John B. Halbert
发明人： Kuljit S. Bains , John B. Halbert
IPC分类号： H03M13/05
CPC分类号： G06F11/1048
摘要： Techniques and mechanisms for providing state information describing one or more data errors detected locally at a memory device. In an embodiment, the memory device includes a memory core and error detection circuit logic configured to detect for errors of data stored by the memory core. A die of the memory device includes both the memory core and the error detection circuitry. In another embodiment, state information is stored in a mode register of the memory device in response to the error detection logic detecting an occurrence of a data error. The state information is available for access by a memory controller or other agent which is external to the memory device.
摘要翻译：用于提供描述在存储器设备本地检测的一个或多个数据错误的状态信息的技术和机制。在一个实施例中，存储器件包括存储器核心和错误检测电路逻辑，其被配置为检测由存储器核心存储的数据的错误。存储器件的管芯包括存储器核心和错误检测电路。在另一个实施例中，响应于错误检测逻辑检测数据错误的发生，将状态信息存储在存储器件的模式寄存器中。状态信息可用于由存储器设备外部的存储器控制器或其他代理进行访问。

35. 发明申请

US20140372816A1 ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE 有权
标题翻译：访问存储在命令/地址寄存器设备中的数据
公开(公告)号：US20140372816A1
公开(公告)日：2014-12-18
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
IPC分类号： G06F11/10 , G06F11/16 , G11C29/44
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译：通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。然后主机处理器从存储器件的寄存器读取信息。

36. 发明授权

US08909856B2 Fast exit from self-refresh state of a memory device 有权
标题翻译：快速退出存储设备的自刷新状态
公开(公告)号：US08909856B2
公开(公告)日：2014-12-09
申请号：US13784356
申请日：2013-03-04
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： G06F13/00 , G11C11/406 , G11C7/22
CPC分类号： G11C11/40615 , G11C7/22 , G11C7/222 , G11C11/406 , G11C2207/2227 , G11C2211/4067
摘要： A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition.
摘要翻译：系统提供信号以指示存储器件何时退出自刷新。因此，基本上在存储器件退出自刷新的同时（之前或之后），可以触发指示符信号以指示存储器件的正常操作或标准刷新操作和正常存储器访问。存储器控制器可以访问指示符信号以确定存储器件是否处于自刷新状态。因此，存储器控制器可以更仔细地管理向存储器件发送命令的定时，同时减少通常与检测自刷新条件相关联的延迟时间。

37. 发明申请

US20140181390A1 METHOD, APPARATUS AND SYSTEM FOR EXCHANGING COMMUNICATIONS VIA A COMMAND/ADDRESS BUS 有权
标题翻译：用于通过命令/地址总线交换通信的方法，装置和系统
公开(公告)号：US20140181390A1
公开(公告)日：2014-06-26
申请号：US13725820
申请日：2012-12-21
申请人： Kuljit S. Bains , James A. McCall
发明人： Kuljit S. Bains , James A. McCall
IPC分类号： G06F12/00 , G11C7/10
CPC分类号： G06F12/00 , G06F13/4243 , G11C7/1045 , G11C7/1072 , G11C7/109 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/4093
摘要： Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command during a first sample period and samples a second portion of the command during a second sample period, the first portion and second portion exchanged via the command/address bus. The first sample period and the second sample period are concurrent with, respectively, a first transition of a clock signal and a second transition of the clock signal. In another embodiment, a mode of the memory device determines a relationship between the first transition and the second transition.
摘要翻译：通过命令/地址总线将信息从存储器控制器交换到存储器件的技术和机制。在一个实施例中，存储器件在第一采样周期期间对命令的第一部分进行采样，并在第二采样周期期间对命令的第二部分进行采样，第一部分和第二部分经由命令/地址总线交换。第一采样周期和第二采样周期分别与时钟信号的第一次转换和时钟信号的第二转换同时进行。在另一个实施例中，存储器装置的模式确定第一转变和第二转换之间的关系。

38. 发明授权

US08738993B2 Memory device on the fly CRC mode 有权
标题翻译：内存设备处于快速CRC模式
公开(公告)号：US08738993B2
公开(公告)日：2014-05-27
申请号：US12978014
申请日：2010-12-23
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： G11C29/00
CPC分类号： H03M13/09 , G06F11/1052 , H03M13/6505
摘要： On the fly enabling and disabling of error detection for memory access transactions on a transaction basis is provided. Dynamic enabling and disabling of error detection for memory access transactions can also be applied for multiple transactions. Control logic associated with the memory device determines whether to apply error detection, and selectively enables error detection in the memory access transaction. The selective enabling of error detection in a memory access transaction can apply to either reads or writes.
摘要翻译：提供了在事务基础上快速启用和禁用内存访问事务的错误检测。动态启用和禁用内存访问事务的错误检测也可以应用于多个事务。与存储器件相关联的控制逻辑确定是否应用错误检测，并且选择性地启用存储器访问事务中的错误检测。存储器访问事务中的错误检测的选择性启用可以应用于读取或写入。

39. 发明申请

US20140095780A1 DISTRIBUTED ROW HAMMER TRACKING 有权
标题翻译：分布式路径追踪
公开(公告)号：US20140095780A1
公开(公告)日：2014-04-03
申请号：US13631781
申请日：2012-09-28
申请人： Kuljit S. Bains , John B. Halbert
发明人： Kuljit S. Bains , John B. Halbert
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G11C11/406 , G11C11/40611 , G11C11/4078
摘要： A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
摘要翻译：存储器控制器响应于分布式检测器的检测器发出目标刷新命令。存储器装置包括检测逻辑，该检测逻辑监视行敲击事件，该行敲击事件是对时间阈值内可能导致数据损坏到物理相邻行（“受害者”行）的行的阈值数量。存储器件向存储器控制器发送行锤事件的指示。响应于行锤事件指示，存储器控制器将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

40. 发明授权

US08649229B2 Memory module bus termination voltage (VTT) regulation and management 有权
标题翻译：内存模块总线终端电压（VTT）的调节和管理
公开(公告)号：US08649229B2
公开(公告)日：2014-02-11
申请号：US13172795
申请日：2011-06-29
申请人： George Vergis , Kuljit S. Bains
发明人： George Vergis , Kuljit S. Bains
IPC分类号： G11C5/14
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1063
摘要： Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了存储器模块总线终端电压（VTT）调节和管理技术和配置。一种方法包括通过寄存器将通过总线驱动的信号接收到包括多个存储器单元的存储器件，并且根据该信号在寄存器内设置总线的终端电压（VTT）。可以描述和/或要求保护其他实施例。

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