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31. 发明申请

US20100230741A1 SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC 审中-公开
标题翻译：具有气隙隔离绝缘电介质的半导体器件
公开(公告)号：US20100230741A1
公开(公告)日：2010-09-16
申请号：US12711033
申请日：2010-02-23
申请人： Jongwan Choi , Eunkee Hong , Bo-Young Lee , Tae-Jong Han , Juseon Goo , Kyungmun Byun
发明人： Jongwan Choi , Eunkee Hong , Bo-Young Lee , Tae-Jong Han , Juseon Goo , Kyungmun Byun
IPC分类号： H01L29/792 , H01L29/06
CPC分类号： H01L29/7881 , H01L21/76229 , H01L21/764 , H01L27/11521 , H01L27/11531 , H01L27/11568 , H01L29/0649
摘要： A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region.
摘要翻译：隧道绝缘层和电荷存储层依次层叠在基板上。凹陷区域穿透电荷存储层，隧道绝缘层和基底的一部分。凹陷区域由底表面和从底表面延伸的侧表面限定。第一电介质图案包括覆盖底面的底部和从底部延伸并覆盖凹部区域的侧表面的一部分的内壁。第二电介质图案位于第一电介质图案的内壁之间的凹陷区域中，并且第二电介质图案包围气隙。由第二电介质图案包围的空气间隙可以沿着远离凹部区域的底表面的方向延伸穿过第二电介质图案的主要部分。

32. 发明申请

US20100167490A1 Method of Fabricating Flash Memory Device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US20100167490A1
公开(公告)日：2010-07-01
申请号：US12629920
申请日：2009-12-03
申请人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
发明人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
IPC分类号： H01L21/762
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.
摘要翻译：提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间与多个单元栅极线相对的线。在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。可以在形成间隔物的空间中形成第二绝缘层。

33. 发明申请

US20090012221A1 COMPOSITIONS INCLUDING PERHYDRO-POLYSILAZANE USED IN A SEMICONDUCTOR MANUFACTURING PROCESS 审中-公开
标题翻译：包括在半导体制造工艺中使用的多晶硅烷的组合物
公开(公告)号：US20090012221A1
公开(公告)日：2009-01-08
申请号：US12194313
申请日：2008-08-19
申请人： Eunkee Hong , Kyu-Tae Na , Ju-Seon Goo , Hong-Gun Kim
发明人： Eunkee Hong , Kyu-Tae Na , Ju-Seon Goo , Hong-Gun Kim
IPC分类号： C08K5/06 , C08L83/08
CPC分类号： H01L21/3125 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02337 , H01L21/316 , H01L21/31695 , H01L21/76232 , H01L21/76837
摘要： A film is formed on a substrate including conductive patterns or trenches using a composition that included a solvent and perhydro-polysilazane having a weight average molecular weight of about 1,800 to 3,000 and a molecular weight distribution of more than about 2.2 to about 3.0. The film is changed into a silicon oxide film, and then an opening is formed through the silicon oxide film. A contact is formed in the opening by filling the opening with conductive material. The silicon oxide film of perhydro-polysilazane having low molecular weight becomes dense and uniform.
摘要翻译：使用包含重量平均分子量约1,800至3,000且分子量分布大于约2.2至约3.0的溶剂和全氢化聚硅氮烷的组合物在包括导电图案或沟槽的基材上形成膜。将膜变成氧化硅膜，然后通过氧化硅膜形成开口。通过用导电材料填充开口在开口中形成接触。具有低分子量的全氢聚硅氮烷的氧化硅膜变得致密且均匀。

34. 发明申请

US20060054989A1 Semiconductor devices having multilayer isolation structures and methods of forming semiconductor devices having multilayer isolation structures 有权
标题翻译：具有多层隔离结构的半导体器件和形成具有多层隔离结构的半导体器件的方法
公开(公告)号：US20060054989A1
公开(公告)日：2006-03-16
申请号：US11209879
申请日：2005-08-23
申请人： Hong-Gun Kim , Eunkee Hong , Kyu-Tae Na
发明人： Hong-Gun Kim , Eunkee Hong , Kyu-Tae Na
IPC分类号： C23C16/00
CPC分类号： C23C16/45523 , C23C16/045 , C23C16/401
摘要： A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially smaller than a width of the recess. Methods of manufacturing a semiconductor device include providing a first structure having a recess in a deposition chamber and flowing first and second reactants over the first structure for a first period at first and second flow rates. Then, the flow rates of the first second reactants to the first structure are substantially reduced for a pause period. The first and second reactants are then flowed over the first structure for a second period at third and fourth flow rates. The deposition and pause steps may be repeated until a multilayer having a desired thickness is formed.
摘要翻译：半导体器件包括具有底部和相对侧表面的凹部的第一结构以及保形地设置在凹部的底部和侧表面上的第二结构。第二结构包括具有两个层的多层，其厚度基本上小于凹部的宽度。制造半导体器件的方法包括提供在沉积室中具有凹槽的第一结构，并且使第一和第二反应物以第一和第二流速在第一结构上流动第一期间。然后，第一第二反应物对第一结构的流速在暂停时间段内显着降低。然后将第一和第二反应物以第三和第四流速在第一结构上流动第二时段。可以重复沉积和暂停步骤，直到形成具有期望厚度的多层。

35. 发明申请

US20050130439A1 Methods of forming spin-on-glass insulating layers in semiconductor devices and associated semiconductor device 失效
标题翻译：在半导体器件和相关半导体器件中形成自旋玻璃绝缘层的方法
公开(公告)号：US20050130439A1
公开(公告)日：2005-06-16
申请号：US11010223
申请日：2004-12-10
申请人： Juseon Goo , Eunkee Hong , Hong-Gun Kim , Kyu-Tae Na
发明人： Juseon Goo , Eunkee Hong , Hong-Gun Kim , Kyu-Tae Na
IPC分类号： H01L21/31 , H01L21/316 , H01L21/60 , H01L21/768 , H01L21/4763 , H01L21/469
CPC分类号： H01L21/02164 , H01L21/02175 , H01L21/022 , H01L21/0228 , H01L21/02318 , H01L21/316 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L21/76897
摘要： Methods of forming an insulating layer in a semiconductor device are provided in which a metal oxide layer is formed on a semiconductor structure that includes a plurality of gap regions thereon. A spin-on-glass layer is formed on the metal oxide layer, and then the semiconductor structure is heated to a temperature of at least about 400° C. The spin-on-glass layer may comprise a siloxane-based material, a silanol-based material or a silazane-based material.
摘要翻译：提供了在半导体器件中形成绝缘层的方法，其中在其上包括多个间隙区域的半导体结构上形成金属氧化物层。在金属氧化物层上形成旋涂玻璃层，然后将半导体结构加热到至少约400℃的温度。旋涂玻璃层可以包括基于硅氧烷的材料，硅烷醇的材料或硅氮烷基材料。

36. 发明授权

US08927389B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08927389B2
公开(公告)日：2015-01-06
申请号：US13369476
申请日：2012-02-09
申请人： Kyungmun Byun , Byoungdeog Choi , Eunkee Hong , Mansug Kang
发明人： Kyungmun Byun , Byoungdeog Choi , Eunkee Hong , Mansug Kang
IPC分类号： H01L21/00 , H01L27/105 , H01L27/108 , H01L29/94 , H01L21/762 , H01L27/115
CPC分类号： H01L21/76229 , H01L27/1052 , H01L27/10894 , H01L27/11531 , H01L29/945
摘要： A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region, forming a first trench having a first width in the first region and a second trench having a second width in the second region, and the second width is greater than the first width. The method also includes forming a first insulation layer in the first and second trenches, removing the first insulation layer in the second trench to form a first insulation pattern that includes the first insulation layer remaining in the first trench, forming on the substrate a second insulation layer that fills the second trench, and the second insulation layer includes a different material from the first insulation layer.
摘要翻译：一种制造半导体器件的方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成具有第一宽度的第一沟槽和在第二区域中具有第二宽度的第二沟槽，第二宽度为大于第一宽度。该方法还包括在第一沟槽和第二沟槽中形成第一绝缘层，去除第二沟槽中的第一绝缘层以形成第一绝缘图案，其包括残留在第一沟槽中的第一绝缘层，在衬底上形成第二绝缘层层，其填充第二沟槽，并且第二绝缘层包括与第一绝缘层不同的材料。

37. 发明申请

US20130095637A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20130095637A1
公开(公告)日：2013-04-18
申请号：US13586325
申请日：2012-08-15
申请人： Honggun KIM , Seung-Heon Lee , Mansug Kang , ByeongJu Bae , Eunkee Hong
发明人： Honggun KIM , Seung-Heon Lee , Mansug Kang , ByeongJu Bae , Eunkee Hong
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of fabricating a semiconductor device, the method including forming a mask layer on a semiconductor substrate; forming a trench in the semiconductor substrate using the mask layer as an etch mask; forming a first layer in the trench; and performing a first thermal treatment process on the first layer such that the first thermal treatment process is performed under an atmosphere that includes ozone and water vapor and transforms the first layer into a second layer.
摘要翻译：一种制造半导体器件的方法，所述方法包括在半导体衬底上形成掩模层; 在所述半导体衬底中使用所述掩模层作为蚀刻掩模形成沟槽; 在沟槽中形成第一层; 以及在所述第一层上进行第一热处理工艺，使得所述第一热处理工艺在包括臭氧和水蒸气的气氛下进行，并将所述第一层转化为第二层。

38. 发明授权

US08026147B2 Method of fabricating a semiconductor microstructure 有权
标题翻译：制造半导体微结构的方法
公开(公告)号：US08026147B2
公开(公告)日：2011-09-27
申请号：US12856262
申请日：2010-08-13
申请人： Yongsoon Choi , Kyung-moon Byun , Eunkee Hong , Eun-kyung Baek
发明人： Yongsoon Choi , Kyung-moon Byun , Eunkee Hong , Eun-kyung Baek
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L21/31111 , H01L27/10817 , H01L27/10852
摘要： Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.
摘要翻译：提供一种制造半导体微结构的方法，该方法包括在半导体衬底上形成下部材料层，该下部材料层包括III族元素的氮化物; 在下部材料层上形成模具材料层; 在所述模具材料层上形成蚀刻掩模，所述蚀刻掩模用于在所述模具材料层中形成结构; 通过使用蚀刻掩模对模具材料层和下部材料层进行各向异性蚀刻; 并对模具材料层和下部材料层进行各向同性蚀刻。

39. 发明授权

US07601588B2 Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same 有权
标题翻译：形成沟槽隔离层的方法和使用其形成非易失性存储器件的方法
公开(公告)号：US07601588B2
公开(公告)日：2009-10-13
申请号：US11267360
申请日：2005-11-04
申请人： Jong-Wan Choi , Hong-Gun Kim , Kyu-Tae Na , Eunkee Hong
发明人： Jong-Wan Choi , Hong-Gun Kim , Kyu-Tae Na , Eunkee Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76232 , H01L27/115
摘要： In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.
摘要翻译：在形成用于最小化寄生电容器的器件隔离层和使用其的非易失性存储器件的方法中，在衬底上形成沟槽。第一绝缘层形成在衬底的顶表面和沟槽的内表面上，使得沟槽部分地被第一绝缘层填充。在第一绝缘层上形成第二绝缘层至填充沟槽的厚度，从而形成预备隔离层。第二绝缘层的蚀刻速率与第一绝缘层的蚀刻速率不同。通过部分去除第一绝缘层和第二绝缘层，在预隔离层的中心部分处形成凹部，从而形成包括凹部的器件隔离层。器件隔离层中的凹槽降低了非易失性存储器件中的寄生电容。

40. 发明授权

US07585786B2 Methods of forming spin-on-glass insulating layers in semiconductor devices and associated semiconductor device 失效
标题翻译：在半导体器件和相关半导体器件中形成自旋玻璃绝缘层的方法
公开(公告)号：US07585786B2
公开(公告)日：2009-09-08
申请号：US11010223
申请日：2004-12-10
申请人： Juseon Goo , Eunkee Hong , Hong-Gun Kim , Kyu-Tae Na
发明人： Juseon Goo , Eunkee Hong , Hong-Gun Kim , Kyu-Tae Na
IPC分类号： H01L21/31
CPC分类号： H01L21/02164 , H01L21/02175 , H01L21/022 , H01L21/0228 , H01L21/02318 , H01L21/316 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L21/76897
摘要： Methods of forming an insulating layer in a semiconductor device are provided in which a metal oxide layer is formed on a semiconductor structure that includes a plurality of gap regions thereon. A spin-on-glass layer is formed on the metal oxide layer, and then the semiconductor structure is heated to a temperature of at least about 400° C. The spin-on-glass layer may comprise a siloxane-based material, a silanol-based material or a silazane-based material.
摘要翻译：提供了在半导体器件中形成绝缘层的方法，其中在其上包括多个间隙区域的半导体结构上形成金属氧化物层。在金属氧化物层上形成旋涂玻璃层，然后将半导体结构加热到至少约400℃的温度。旋涂玻璃层可以包括基于硅氧烷的材料，硅烷醇的材料或硅氮烷基材料。

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