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31. 发明授权

US5451890A Gallium arsenide source follower FET logic family with diodes for preventing leakage currents 失效
标题翻译：砷化镓源极跟随器FET逻辑系列具有防止漏电流的二极管
公开(公告)号：US5451890A
公开(公告)日：1995-09-19
申请号：US225518
申请日：1994-04-11
申请人： Alain J. Martin , Jose A. Tierno , Brian Von Herzen
发明人： Alain J. Martin , Jose A. Tierno , Brian Von Herzen
IPC分类号： H03K19/0952 , H03K19/0956
CPC分类号： H03K19/0952
摘要： The basic building block of the invention is an inverter gate consisting of two stages: The first stage is an input logic switching stage consisting of a depletion mode pull-up FET whose gate is the input node and whose source-to-drain channel is connected in series through a level-shifting Schottky diode with the source-to-drain channel of an depletion mode pull-down FET between drain and source voltage rails. The source of the pull-up FET is connected to the diode's anode while the drain of the pull-down FET is connected to the diode's cathode and is the output node of the input logic switching stage. The level-shifting diode isolates the output node from the input node, which allows the input voltage to switch rail-to-rail without causing problems. The voltage between the source and drain rails is selected so that the Schottky barrier gate of the enhancement mode pull-up transistor is barely forward biased over the threshold voltage of the Schottky barrier gate junction, so that there is very little current through the gate. The second stage is an inverting stage having an enhancement mode pull-up transistor and a depletion mode pull-down transistor whose source-to-drain channels are connected in series across the source and drain voltage rails. The gate of the pull down transistor is connected to the output node of the logic switching stage, while the source-to-drain connection between the two transistors is the output node of the gate.
摘要翻译：本发明的基本构造块是由两个阶段组成的反相器门：第一级是由耗尽型上拉FET组成的输入逻辑开关级，其栅极是输入节点并且源极 - 漏极通道连接通过电平移位肖特基二极管串联，在漏极和源极电压轨之间具有耗尽型下拉FET的源极到漏极通道。上拉FET的源极连接到二极管的阳极，而下拉FET的漏极连接到二极管的阴极，并且是输入逻辑开关级的输出节点。电平移位二极管将输出节点与输入节点隔离，这允许输入电压切换轨到轨而不会引起问题。选择源极和漏极之间的电压，使得增强模式上拉晶体管的肖特基势垒栅极不会在肖特基势垒栅极结的阈值电压上正向偏置，使得通过栅极的电流非常小。第二级是具有增强型上拉晶体管和耗尽型下拉晶体管的反相级，其源极至漏极通道串联连接在源极和漏极电压轨道上。下拉晶体管的栅极连接到逻辑开关级的输出节点，而两个晶体管之间的源极到漏极连接是栅极的输出节点。

32. 发明授权

US08898097B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
标题翻译：可重构和可定制的神经网络通用电路
公开(公告)号：US08898097B2
公开(公告)日：2014-11-25
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

33. 发明授权

US08856055B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
公开(公告)号：US08856055B2
公开(公告)日：2014-10-07
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

34. 发明授权

US08704566B2 Hybrid phase-locked loop architectures 有权
标题翻译：混合锁相环架构
公开(公告)号：US08704566B2
公开(公告)日：2014-04-22
申请号：US13608277
申请日：2012-09-10
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.
摘要翻译：提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

35. 发明申请

US20140070856A1 HYBRID PHASE-LOCKED LOOP ARCHITECTURES 有权
标题翻译：混合相位锁定环路结构
公开(公告)号：US20140070856A1
公开(公告)日：2014-03-13
申请号：US13611008
申请日：2012-09-12
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/107
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.
摘要翻译：提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

36. 发明申请

US20120317062A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
标题翻译：神经网络可重构和可定制的一般用途电路
公开(公告)号：US20120317062A1
公开(公告)日：2012-12-13
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

37. 发明申请

US20120084241A1 PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
标题翻译：在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性
公开(公告)号：US20120084241A1
公开(公告)日：2012-04-05
申请号：US12895791
申请日：2010-09-30
申请人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

38. 发明申请

US20100188158A1 OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL 有权
标题翻译：数字控制振荡器的最佳抖动，具有时钟抖动，用于增益和带宽控制
公开(公告)号：US20100188158A1
公开(公告)日：2010-07-29
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/099
CPC分类号： H03L7/081 , H03L7/085 , H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译：数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。

39. 发明申请

US20100013532A1 PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING MULTIPLEXER CIRCUIT FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS 失效
标题翻译：相位锁定环路和数字控制振荡器微调控制的多路复用器电路实现方法
公开(公告)号：US20100013532A1
公开(公告)日：2010-01-21
申请号：US12173159
申请日：2008-07-15
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/08
CPC分类号： H03L7/093 , H03L7/099 , H03L7/107 , H03L2207/50
摘要： Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.
摘要翻译：提供了电路和方法，其中数字PLL电路中的DCO（数字控制振荡器）电路的微调控制通过在数字控制下对多路复用器电路进行抖动控制来实现，以选择性地输出具有变化的电压电平的多个模拟控制电压中的一个输入到DCO的分数频率控制端口，以分数频率分辨率驱动DCO的调谐元件，并在模拟控制下实现DCO的连续微调。

40. 发明授权

US06650699B1 Methods and apparatus for timing recovery from a sampled and equalized data signal 有权
标题翻译：用于从采样和均衡的数据信号定时恢复的方法和装置
公开(公告)号：US06650699B1
公开(公告)日：2003-11-18
申请号：US09234767
申请日：1999-01-21
申请人： Jose A. Tierno
发明人： Jose A. Tierno
IPC分类号： H03H730
CPC分类号： H04L7/0062 , H03L7/091 , H03L7/0995 , H04L7/0058
摘要： Methods and apparatus for use in a communication channel receiver for generating a sampling phase error signal for adjustment of a sampling clock signal associated with the receiver are provided. In an illustrative embodiment, a method includes generating a signal representative of a weighted linear combination of a predetermined number of samples of a received input signal. The combination is a function of the samples and tap-weights of a finite impulse response filter associated with the receiver. Next, the illustrative method includes generating an error signal representative of the difference between an equalized sequence of samples of the received input signal and a decoded sequence of samples of the received input signal. Still further, the illustrative method includes multiplying the weighted linear combination signal with the error signal to generate a phase error signal. The phase error signal is then used to generate a phase correction signal for subsequent application to the sampling clock signal. Such application serves to adjust the sampling clock signal associated with the receiver such that the sampling clock signal substantially matches a data rate associated with the input signal.
摘要翻译：提供了一种在通信信道接收机中用于生成用于调整与接收机相关联的采样时钟信号的采样相位误差信号的方法和装置。在说明性实施例中，一种方法包括生成表示接收到的输入信号的预定数量样本的加权线性组合的信号。该组合是与接收器相关联的有限脉冲响应滤波器的样本和抽头权重的函数。接下来，说明性方法包括生成表示所接收的输入信号的均衡采样序列与接收到的输入信号的解码采样序列之间的差的误差信号。此外，说明性方法包括将加权线性组合信号与误差信号相乘以产生相位误差信号。然后使用相位误差信号产生相位校正信号，以便随后应用于采样时钟信号。这种应用用于调整与接收机相关联的采样时钟信号，使得采样时钟信号基本上与输入信号相关联的数据速率匹配。

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