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31. 发明公开

EP0964447A1 Self-aligned local interconnection for cmos and its manufacturing method 有权
标题翻译：针对CMOS和ihr Herstellungsverfahren的Selbstjustierende lokale Zwischenverbindung
公开(公告)号：EP0964447A1
公开(公告)日：1999-12-15
申请号：EP99301698.9
申请日：1999-03-08
申请人： Sharp Kabushiki Kaisha , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Hsu, Sheng Teng
IPC分类号： H01L21/768 , H01L21/285 , H01L21/8238
CPC分类号： H01L21/32053 , H01L21/28518 , H01L21/76895 , H01L21/823814 , H01L21/823835 , H01L21/823871
摘要： An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.
摘要翻译：通过周围的场氧化物通过硅化物连接到CMOS晶体管的源极/漏极区域，从而可以将晶体管连接到晶体管，而不会直接接触其源极/漏极区域，从而可以使其更小。通过以下步骤，通过使用栅极电极第二侧壁结构从具有源极/漏极区域的至少第一晶体管形成互连的方法：（a）在下部栅极氧化物层和氧化物侧壁的一部分上形成栅电极（42）源/漏区; （b）在包括（a）和周围场氧化物（50,52）的晶体管上沉积半导体膜（72），然后沉积绝缘膜; （c）各向异性地蚀刻绝缘体以将其从源极/漏极，栅电极和周围的场氧化物区域移除，而不是从侧壁排出，从而形成第二侧壁; （d）在所述半导体，源极/漏极和场氧化物的选定区域上沉积难熔金属（78）; 和（e）对半导体和难熔金属进行退火以在源极/漏极和选定的场氧化物区域上形成硅化物膜（80），并在它们之间形成电互连，以使源极/漏极区域的尺寸最小化。

32. 发明公开

EP0936664A2 Partial silicidation method to form shallow source/drain junctions 有权
标题翻译： Teilsilizidierungsverfahren到浅源/漏结的形成
公开(公告)号：EP0936664A2
公开(公告)日：1999-08-18
申请号：EP99300474.6
申请日：1999-01-22
申请人： SHARP KABUSHIKI KAISHA , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Maa, Jer-Shen , Hsu, Sheng Teng , Peng, Chien-Hsiung
IPC分类号： H01L21/60 , H01L21/336 , H01L29/08 , H01L21/265 , H01L29/78
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665 , H01L29/6659
摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.

33. 发明公开

EP0929105A2 Metal gate sub-micron mos transistor and method of making same 审中-公开
标题翻译：金属栅极亚微米MOS晶体管和赫特尔肺癌的方法
公开(公告)号：EP0929105A2
公开(公告)日：1999-07-14
申请号：EP99300130.4
申请日：1999-01-08
申请人： Sharp Kabushiki Kaisha , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Hsu, Sheng Teng , Nguyen, Tue , Evans, David R.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/28088 , H01L21/28097 , H01L21/76895 , H01L21/76897 , H01L21/82385 , H01L29/42376 , H01L29/4966 , H01L29/4975 , H01L29/66545
摘要： A MOS transistor is formed on a single crystal silicon substrate doped to form a conductive layer of a first type, and includes: an active region formed on said substrate; a source region and a drain region located in said active region, doped to form conductive channels of a second type; a metal gate region located in said active region between said source region and said drain region, wherein said metal gate has a width of less than one micron; a gate oxide region located over said gate region; an oxide region located over the structure; and a source electrode, a gate electrode and a drain electrode, each connected to their respective regions, and each formed of a combination of a contact metal and an electrode metal. An alternate embodiment includes a pair of MOS transistors which have an interconnect between their gate electrodes and the drain electrode of one transistor and the drain electrode of the other transistor.

34. 发明公开

EP0892428A2 Method of producing low resistance contacts between integrated circuit metal levels and structure produced thereby. 失效
标题翻译：一种用于制造具有由此产生的集成电路的金属化层和结构之间的低电阻接触的方法
公开(公告)号：EP0892428A2
公开(公告)日：1999-01-20
申请号：EP98305610.2
申请日：1998-07-15
申请人： Sharp Kabushiki Kaisha , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Nguyen, Tue , Hsu, Sheng Teng
IPC分类号： H01L21/768 , H01L21/285
CPC分类号： H01L21/76844 , H01L21/28568 , H01L21/76801 , H01L21/76807 , H01L21/76831 , H01L21/76838 , H01L21/76865 , H01L23/5226 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.
摘要翻译：形成直接的，铜 - 铜，电平之间在IC连接的方法是游离缺失盘。经由互连A通过各向同性在经由通过绝缘体上沉积阻挡材料，以较低的铜水平，然后各向异性的经由蚀刻去除覆盖所述下一级铜阻挡材料形成。各向异性蚀刻离开穿过绝缘体衬经由阻挡材料。随后沉积的上层金属随后直接接触下一级铜当通过被填充。双镶嵌互连是通过在绝缘体上互连沟槽的蚀刻和各向异性沉积在沟槽底部的非导电性阻障层材料形成。然后通过从沟槽互连到较低水平的铜形成。如上所述，导电阻挡材料各向同性地沉积在沟槽/过孔结构，以及各向异性地蚀刻以去除覆盖所述下一级铜阻挡材料。绝缘阻挡层材料，衬着沟槽和通过，仍然存在。经由互连结构的IC和双镶嵌互连结构，在雅舞蹈用上述方法制备的，所提供的。

35. 发明授权

EP1246231B1 Electrode materials with improved hydrogen degradation resistance and fabrication method 有权
标题翻译：具有改进的Wasserstoffdegradationswiderstand和制造方法的电极材料
公开(公告)号：EP1246231B1
公开(公告)日：2010-06-16
申请号：EP02006830.0
申请日：2002-03-25
申请人： Sharp Kabushiki Kaisha
发明人： Zhang, Fengyan , Li, Tingkai , Ying, Hong , Ono, Yoshi , Hsu, Sheng Teng
IPC分类号： H01L21/02 , H01L21/316
CPC分类号： H01L28/75 , H01L21/31604 , H01L21/31683 , H01L28/55

36. 发明授权

EP1441391B1 Dual-trench isolated crosspoint memory array and method for fabricating same 有权转让
标题翻译：双严重孤立的交叉点存储器阵列及其制造方法
公开(公告)号：EP1441391B1
公开(公告)日：2008-11-26
申请号：EP03258165.4
申请日：2003-12-24
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Pan, Wei , Zhuang, Weiwei
IPC分类号： H01L27/10
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/101 , H01L27/24

37. 发明授权

EP1498952B1 Oxygen content system and method for controlling memory resistance properties 有权转让
标题翻译：系统具有受控的氧含量和方法用于控制存储器器件的电阻特性
公开(公告)号：EP1498952B1
公开(公告)日：2008-01-30
申请号：EP04011966.1
申请日：2004-05-19
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Zhang, Fengyan
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L27/016 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641

38. 发明公开

EP1302978A3 Method of making a self-aligned ferroelectric memory transistor 审中-公开
标题翻译：一种制造自对准的存储器晶体管ferrroelektrischen的方法
公开(公告)号：EP1302978A3
公开(公告)日：2008-01-09
申请号：EP02023155.1
申请日：2002-10-15
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Li, Tingkai , Zhang, Fengyan
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/51 , H01L21/28291 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L29/516
摘要： A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.

39. 发明公开

EP1498945A3 Low power flash memory cell and method 审中-公开
标题翻译：闪存单元和方法的较低的功率消耗
公开(公告)号：EP1498945A3
公开(公告)日：2007-09-26
申请号：EP04016720.7
申请日：2004-07-15
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Ono, Yoshi
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L29/788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883 , Y10S438/975
摘要： Flash memory cells are provided with a high-k dielectric material interposed between a floating polysilicon gate and a control gate. A tunnel oxide layer is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided, comprising the steps of: forming a first polysilicon layer over a substrate, forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer, depositing a second polysilicon layer over the oxide layer, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, the exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.

40. 发明授权

EP1035589B1 Iridium composite barrier structure and method for same 有权
标题翻译：铱复合阻挡结构和它们的制备方法
公开(公告)号：EP1035589B1
公开(公告)日：2007-05-02
申请号：EP00301790.2
申请日：2000-03-06
申请人： SHARP KABUSHIKI KAISHA , Sharp Laboratories of America, Inc.
发明人： Zhang, Fengyan , Maa, Jer-Shen , Hsu, Sheng Teng
IPC分类号： H01L29/45 , H01L21/28
CPC分类号： H01L28/75 , H01L21/28291 , H01L28/55 , H01L29/516

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