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    • 34. 发明授权
    • Apparatus for managing page zero accesses in a multi-processor data
processing system
    • 用于在多处理器数据处理系统中管理页面零访问的装置
    • US5337416A
    • 1994-08-09
    • US154675
    • 1993-11-18
    • Robert P. RyanJohn B. CrowtherRobert A. MacDonald
    • Robert P. RyanJohn B. CrowtherRobert A. MacDonald
    • G06F12/00G06F12/02G06F15/16G06F15/167
    • G06F12/0284
    • Apparatus for use in a multi-CPU data processing system (10) wherein each CPU (12-18) is coupled to a common bus (20) and through the common bus to a main memory (28). The apparatus provides a program, such as an operating system, that is operating upon each of the CPUs access to a page of data within the main memory. Each of the CPUs generates a first address for identifying a memory location or locations within a page of the main memory. The first address is modified as a function of the first address and as a function of an identification of the CPU to generate a second address for identifying a memory location or locations that are either within the same page or within another page of the main memory. The modified second address is applied to the memory for accessing the memory location or locations.
    • 一种用于多CPU数据处理系统(10)的装置,其中每个CPU(12-18)耦合到公共总线(20),并通过公共总线耦合到主存储器(28)。 该装置提供了一个程序,例如操作系统,其操作在每个CPU上访问主存储器内的一页数据。 每个CPU产生用于识别主存储器的页面内的存储器位置或位置的第一地址。 第一地址被修改为第一地址的函数,并且作为CPU的标识的函数,以生成用于标识存储器位置的第二地址或位于相同页面内或在主存储器的另一页内的位置。 修改的第二地址被应用于存储器以访问存储器位置或位置。