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31. 发明申请

US20100138609A1 Technique for controlling computing resources 有权
标题翻译：控制计算资源的技术
公开(公告)号：US20100138609A1
公开(公告)日：2010-06-03
申请号：US12315331
申请日：2008-12-02
申请人： William Hasenplaugh , Joel Emer , Tryggve Fossum , Aamer Jaleel , Simon Steely
发明人： William Hasenplaugh , Joel Emer , Tryggve Fossum , Aamer Jaleel , Simon Steely
IPC分类号： G06F12/00 , G06F9/46
CPC分类号： G06F12/0802 , G06F9/5016 , G06F12/0862 , G06F12/0866 , G06F2209/501 , Y02D10/22
摘要： A technique to enable resource allocation optimization within a computer system. In one embodiment, a gradient partition algorithm (GPA) module is used to continually measure performance and adjust allocation to shared resources among a plurality of data classes in order to achieve optimal performance.
摘要翻译：一种在计算机系统内实现资源分配优化的技术。在一个实施例中，使用梯度分割算法（GPA）模块来连续地测量性能并且调整对多个数据类之间的共享资源的分配，以便实现最佳性能。

32. 发明申请

US20070198872A1 METHOD, SYSTEM, AND APPARATUS FOR IMPROVING MULTI-CORE PROCESSOR PERFORMANCE 有权
标题翻译：用于改进多核处理器性能的方法，系统和装置
公开(公告)号：US20070198872A1
公开(公告)日：2007-08-23
申请号：US11686861
申请日：2007-03-15
申请人： Daniel Bailey , Todd Dutton , Tryggve Fossum
发明人： Daniel Bailey , Todd Dutton , Tryggve Fossum
IPC分类号： G06F1/04
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.
摘要翻译：用于核心配给逻辑以使多核处理器的核能够遵守各种功率和热约束的系统，装置和方法。

33. 发明申请

US20060156153A1 Method of handling errors 有权
标题翻译：处理错误的方法
公开(公告)号：US20060156153A1
公开(公告)日：2006-07-13
申请号：US11012979
申请日：2004-12-14
申请人： Tryggve Fossum , Yaron Shragai , Shubhendu Mukherjee
发明人： Tryggve Fossum , Yaron Shragai , Shubhendu Mukherjee
IPC分类号： H04L1/00 , H03M13/00 , G08C25/00 , G06F11/00 , G06F11/30
CPC分类号： G06F11/0721 , G06F11/0793
摘要： An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.
摘要翻译：处理器的错误处理程序，响应于处理器的第一检测到的不可恢复错误（DUE）执行，响应于通过评估第二DUE对错误处理例程的正确性的影响而发生第二DUE的指示。

34. 发明申请

US20060123264A1 Method, system, and apparatus for improving multi-core processor performance 有权
公开(公告)号：US20060123264A1
公开(公告)日：2006-06-08
申请号：US11336681
申请日：2006-01-20
申请人： Daniel Bailey , Todd Dutton , Tryggve Fossum
发明人： Daniel Bailey , Todd Dutton , Tryggve Fossum
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

35. 发明申请

US20050050310A1 Method, system, and apparatus for improving multi-core processor performance 审中-公开
标题翻译：用于提高多核处理器性能的方法，系统和设备
公开(公告)号：US20050050310A1
公开(公告)日：2005-03-03
申请号：US10621228
申请日：2003-07-15
申请人： Daniel Bailey , Todd Dutton , Tryggve Fossum
发明人： Daniel Bailey , Todd Dutton , Tryggve Fossum
IPC分类号： G06F1/32 , G06F9/00
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.
摘要翻译：用于核心配给逻辑以使多核处理器的核能够遵守各种功率和热约束的系统，装置和方法。

36. 发明授权

US5093775A Microcode control system for digital data processing system 失效
标题翻译：数字数据处理系统MICROCODE控制系统
公开(公告)号：US5093775A
公开(公告)日：1992-03-03
申请号：US549611
申请日：1983-11-07
申请人： William R. Grundmann , Raymond F. Boucher , Tryggve Fossum
发明人： William R. Grundmann , Raymond F. Boucher , Tryggve Fossum
IPC分类号： G06F9/22 , G06F9/28
CPC分类号： G06F9/28
摘要： A microcode control system for a digital data processor. The processor sequentially processes data in response to a microinstruction in a data processing path including a plurality of successive processing stages. A control path parallels the data processing path and includes a plurality of stage which transfer the microinstruction in synchronism with the transfer of data through the data processing path. At each stage in the control path, the microinstruction is decoded to determine the operation to be performed in response thereto on the data by the stage in the data processing path, and control signals are generated to control the processing by the stage in the data processing path.
摘要翻译：一种用于数字数据处理器的微代码控制系统。处理器响应于包括多个连续处理级的数据处理路径中的微指令顺序地处理数据。控制路径平行于数据处理路径并且包括多个级，其通过数据处理路径与数据的传送同步地传送微指令。在控制路径中的每个阶段，对微指令进行解码，以确定响应于该数据处理路径中的阶段对数据执行的操作，并且生成控制信号以控制数据处理中的阶段的处理路径。

37. 发明授权

US4949250A Method and apparatus for executing instructions for a vector processing system 失效
标题翻译：用于执行向量处理系统的指令的方法和装置
公开(公告)号：US4949250A
公开(公告)日：1990-08-14
申请号：US170395
申请日：1988-03-18
申请人： Dileep P. Bhandarkar , Robert Supnik , Tryggve Fossum , Dwight Manley
发明人： Dileep P. Bhandarkar , Robert Supnik , Tryggve Fossum , Dwight Manley
IPC分类号： G06F17/16 , G06F9/318 , G06F15/78
CPC分类号： G06F9/382 , G06F15/8084 , G06F9/30036 , G06F9/3824 , G06F9/3889
摘要： A data processing system containing a vector processor and a scalar processor executes scalar and vector instructions which both comprise an operation portion and an operand pointer portion. In the vector instructions, however, the operand pointer portion contains an operand specifier which identifies a vector control word. Each vector control word contains, for the corresponding vector instruction, flags and vector operand pointers. The vector operand pointers specify vector registers in the vector processor. The flags contain additional information for the execution of the vector instructions.
摘要翻译：包含向量处理器和标量处理器的数据处理系统执行包括操作部分和操作数指针部分的标量和矢量指令。然而，在向量指令中，操作数指针部分包含标识向量控制字的操作数说明符。对于相应的向量指令，每个向量控制字包含标志和向量操作数指针。向量操作数指针在向量处理器中指定向量寄存器。标志包含用于执行向量指令的附加信息。

38. 发明授权

US4583222A Method and apparatus for self-testing of floating point accelerator processors 失效
标题翻译：用于浮点加速器处理器自检的方法和装置
公开(公告)号：US4583222A
公开(公告)日：1986-04-15
申请号：US549612
申请日：1983-11-07
申请人： Tryggve Fossum , Milton L. Shively
发明人： Tryggve Fossum , Milton L. Shively
IPC分类号： G06F7/00 , G06F7/48 , G06F7/76 , G06F11/16 , G06F11/22 , G06F11/27
CPC分类号： G06F11/2273 , G06F11/16 , G06F11/2242 , G06F11/2268 , G06F7/00 , G06F7/483
摘要： A mechanism for continually testing a first processor element in a suitable multiprocessor system in which at least first and second processor elements are connected to a common input bus to concurrently receive the same opcodes and operands. Both processors decode the opcodes; when an opcode indicates an operation to be performed by the second processor, the first processor responds by executing a diagnostic operation during the second processor's execution cycle, instead of remaining idle for that time. The particular diagnostic operation to be performed is selected from among a multiplicity of available diagnostic operations. The selection is dependent on the instruction to be executed by the second processor; that is, in order to not slow down the overall execution rate of the system, a diagnostic operation is chosen whose execution time is somewhat shorter than the execution time of the instruction being performed by the second processor. Operand data supplied for the second processor's operation may be used as test data by at least some of the diagnostic operations for the first processor, to facilitate detection of bits forced to a zero or one value. Both data paths and control logic of the first processor are checked during the execution of each instruction intended for another processor, without slowing overall system response or adding more than an insignificant marginal cost. The diagnostic system is self-executing and is completely transparent to the programmer.
摘要翻译：一种用于在合适的多处理器系统中连续测试第一处理器元件的机构，其中至少第一和第二处理器元件连接到公共输入总线以同时接收相同的操作码和操作数。两个处理器解码操作码; 当操作码指示要由第二处理器执行的操作时，第一处理器通过在第二处理器的执行周期期间执行诊断操作来响应，而不是在该时间内保持空闲。要进行的特定诊断操作从多个可用诊断操作中选择。该选择取决于由第二处理器执行的指令; 也就是说，为了不降低系统的整体执行速度，选择其执行时间比由第二处理器执行的指令的执行时间稍短的诊断操作。为第二处理器的操作提供的操作数据可以被用作第一处理器的至少一些诊断操作的测试数据，以便于检测被强制为零或一个值的位。在执行旨在用于另一处理器的每个指令期间，检查第一处理器的数据路径和控制逻辑，而不会减缓整个系统响应或增加超过一个微不足道的边际成本。诊断系统是自动执行的，对程序员完全透明。

39. 发明授权

US08924690B2 Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction 有权
标题翻译：通过资源分配和限制的异构芯片多处理器的装置和方法
公开(公告)号：US08924690B2
公开(公告)日：2014-12-30
申请号：US13482713
申请日：2012-05-29
申请人： Tryggve Fossum , George Chrysos , Todd A. Dutton
发明人： Tryggve Fossum , George Chrysos , Todd A. Dutton
IPC分类号： G06F9/30 , G06F9/38 , G06F9/50 , G06F1/32
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3287 , G06F9/30181 , G06F9/3802 , G06F9/3869 , G06F9/5061 , G06F9/5094 , Y02D10/171 , Y02D10/22
摘要： A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.
摘要翻译：一种通过资源限制的异构芯片多处理器（CMP）的方法和装置。在一个实施例中，该方法包括访问资源利用寄存器以识别资源利用策略。一旦被访问，处理器控制器确保处理器核心以资源利用策略指定的方式利用共享资源。在一个实施例中，CMP内的每个处理器核心包括指令发布节流阀资源利用寄存器，指令提取节流阀资源利用寄存器以及在最小和最大利用水平内限制其对共享资源的利用的类似方式。在一个实施例中，资源限制提供了将电流和功率资源分配给可由硬件或软件控制的CMP的处理器核心的灵活方式。描述和要求保护其他实施例。

40. 发明授权

US08893094B2 Hardware compilation and/or translation with fault detection and roll back functionality 有权
标题翻译：具有故障检测和回滚功能的硬件编译和/或翻译
公开(公告)号：US08893094B2
公开(公告)日：2014-11-18
申请号：US13341812
申请日：2011-12-30
申请人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
发明人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
IPC分类号： G06F9/45 , G06F7/38 , G06F11/00 , G06F9/38 , G06F9/46 , G06F11/07
CPC分类号： G06F8/44 , G06F9/3001 , G06F9/30087 , G06F9/30174 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/462 , G06F11/0751
摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.
摘要翻译：公开了具有故障检测和回滚功能的硬件编译和/或翻译。编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令通过比较第二操作结果与记录的第一操作结果。在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。

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