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31. 发明授权

US07393718B2 Unmolded package for a semiconductor device 有权
标题翻译：用于半导体器件的未模制封装
公开(公告)号：US07393718B2
公开(公告)日：2008-07-01
申请号：US11202510
申请日：2005-08-11
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L21/44
CPC分类号： H01L23/145 , H01L23/3735 , H01L23/49816 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L25/074 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/45147 , H01L2224/48227 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H05K3/3436 , H01L2924/00 , H01L2924/00015
摘要： A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.
摘要翻译：不包括成型体或封装的半导体器件。半导体器件包括衬底和耦合到衬底的管芯。芯片耦合到衬底，使得假设MOSFET型器件的管芯的源极和栅极区域耦合到衬底。焊球靠近模具设置，使得当半导体器件耦合到印刷电路板时，暴露的表面用作漏极连接，而焊球用作源极和栅极连接。

32. 发明授权

US07332806B2 Thin, thermally enhanced molded package with leadframe having protruding region 有权
标题翻译：薄的，热增强的模制包装，具有突出区域的引线框架
公开(公告)号：US07332806B2
公开(公告)日：2008-02-19
申请号：US11048314
申请日：2005-01-31
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/48 , H01L23/495 , H01L23/34 , H01L29/76
CPC分类号： H01L23/495 , H01L23/49548 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L24/34 , H01L24/37 , H01L2224/16 , H01L2224/16245 , H01L2224/37599 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/37099
摘要： A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.
摘要翻译：半导体管芯封装。其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构耦合到所述第一表面，（c）栅极引线结构耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料。模制材料暴露半导体管芯的第二表面和源极引线结构的主表面。

33. 发明授权

US06992384B2 High performance multi-chip flip chip package 失效
公开(公告)号：US06992384B2
公开(公告)日：2006-01-31
申请号：US10741217
申请日：2003-12-19
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L23/34
CPC分类号： B23K1/0008 , B23K3/0623 , B23K2101/40 , H01L23/492 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

34. 发明申请

US20050280161A1 Unmolded package for a semiconductor device 有权
标题翻译：用于半导体器件的未模制封装
公开(公告)号：US20050280161A1
公开(公告)日：2005-12-22
申请号：US11202510
申请日：2005-08-11
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L23/12 , H01L21/60 , H01L23/14 , H01L23/373 , H01L23/48 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18 , H05K3/34
CPC分类号： H01L23/145 , H01L23/3735 , H01L23/49816 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L25/074 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/45147 , H01L2224/48227 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H05K3/3436 , H01L2924/00 , H01L2924/00015
摘要： A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.
摘要翻译：不包括成型体或封装的半导体器件。半导体器件包括衬底和耦合到衬底的管芯。芯片耦合到衬底，使得假设MOSFET型器件的管芯的源极和栅极区域耦合到衬底。焊球靠近模具设置，使得当半导体器件耦合到印刷电路板时，暴露的表面用作漏极连接，而焊球用作源极和栅极连接。

35. 发明申请

US20050104168A1 Molded leadless package having improved reliability and high thermal transferability, and sawing type molded leadless package and method of manufacturing the same 有权
标题翻译：具有改善的可靠性和高的热转印性的成型无引线封装，以及锯切型模制无引线封装及其制造方法
公开(公告)号：US20050104168A1
公开(公告)日：2005-05-19
申请号：US10987550
申请日：2004-11-12
申请人： Yoon-hwa Choi , Shi-baek Nam , O-seob Jeon , Rajeev Joshi , Maria Estacio
发明人： Yoon-hwa Choi , Shi-baek Nam , O-seob Jeon , Rajeev Joshi , Maria Estacio
IPC分类号： H01L23/31 , H01L23/433 , H01L23/495
CPC分类号： H01L23/4334 , H01L23/3107 , H01L23/315 , H01L23/49568 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L2224/05554 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.
摘要翻译：提供了一种模制无引线封装和锯切型模制无引线封装及其制造方法。模制的无引线封装包括具有彼此相对的第一和第二表面的引线框架焊盘。半导体芯片粘附到引线框架焊盘的第一表面。引线电耦合到半导体芯片。模制材料覆盖引线框架焊盘，半导体芯片和引线，并且暴露引线的一部分和引线框架焊盘的第二表面的一部分。在覆盖引线框架焊盘的第二表面的成型材料的表面与引线框架焊盘本身的第二表面之间形成台阶差。锯切型成型无引线封装包括后形状或凸形并从管芯焊盘的下表面突出的防短路部件。

36. 发明授权

US06633030B2 Surface mountable optocoupler package 失效
标题翻译：表面贴装光耦合器封装
公开(公告)号：US06633030B2
公开(公告)日：2003-10-14
申请号：US09944717
申请日：2001-08-31
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L3100
CPC分类号： H01L31/173 , H01L2224/45144 , H01L2224/48227 , H01L2224/48247 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/14 , H01L2924/3025 , H01L2924/00
摘要： An optocoupler package is disclosed. The optocoupler package comprises a carrier substrate and a plurality of conductive regions on the carrier substrate. An optoelectronic device, an optically transmissive medium, and a plurality of conductive structures can be on the carrier substrate.
摘要翻译：公开了一种光耦合器封装。光耦合器封装包括载体衬底和载体衬底上的多个导电区域。光电子器件，透光介质和多个导电结构可以在载体衬底上

37. 发明授权

US06566749B1 Semiconductor die package with improved thermal and electrical performance 有权
标题翻译：具有改善的热和电性能的半导体管芯封装
公开(公告)号：US06566749B1
公开(公告)日：2003-05-20
申请号：US10050428
申请日：2002-01-15
申请人： Rajeev Joshi , Steven Sapp
发明人： Rajeev Joshi , Steven Sapp
IPC分类号： H01L2310
CPC分类号： H01L24/85 , H01L23/04 , H01L23/3675 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/16152 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.
摘要翻译：公开了一种半导体管芯封装。在一个实施例中，封装包括包括垂直功率晶体管的半导体管芯。源极电极和栅极接触区域位于半导体管芯的第一表面。漏极位于半导体管芯的第二表面。基底构件靠近半导体管芯的第二表面，并且远离半导体管芯的第一表面，并且覆盖设置在半导体管芯的第一表面上。盖子耦合到基座构件并且适于将跳动从半导体管芯移出。

38. 发明授权

US06489678B1 High performance multi-chip flip chip package 失效
标题翻译：高性能多芯片倒装芯片封装
公开(公告)号：US06489678B1
公开(公告)日：2002-12-03
申请号：US09285191
申请日：1999-03-15
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L2334
CPC分类号： B23K1/0008 , B23K3/0623 , B23K2101/40 , H01L23/492 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.
摘要翻译：一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。在每个引线框架中形成的腔内部附着有硅管芯。然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块的阵列来形成硅片的有源表面与印刷电路板的直接连接。

39. 发明授权

US6133634A High performance flip chip package 有权
标题翻译：高性能倒装芯片封装
公开(公告)号：US6133634A
公开(公告)日：2000-10-17
申请号：US129663
申请日：1998-08-05
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： B23K1/00 , B23K3/06 , H01L23/492 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： B23K1/0008 , B23K3/0623 , H01L23/492 , B23K2201/40 , H01L2924/0002
摘要： An improved semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. A silicon die is attached to a carrier (or substrate) that has a cavity substantially surrounding the die. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of the die as well as the edges of the carrier surrounding the die.
摘要翻译：改进的半导体封装，将封装电阻降低到可忽略的水平，并提供出色的散热性能。将硅片连接到具有基本上围绕裸片的空腔的载体（或基底）上。然后通过分布在模具表面以及围绕模具的载体的边缘的焊料凸块的阵列制造硅片的有源表面与印刷电路板的直接连接。

40. 发明申请

US20120326287A1 DC/DC CONVERTOR POWER MODULE PACKAGE INCORPORATING A STACKED CONTROLLER AND CONSTRUCTION METHODOLOGY 审中-公开
标题翻译： DC / DC转换器电源模块包装堆叠控制器和构造方法
公开(公告)号：US20120326287A1
公开(公告)日：2012-12-27
申请号：US13170017
申请日：2011-06-27
申请人： Rajeev Joshi , Jaime A. Bayan , Ashok S. Prabhu
发明人： Rajeev Joshi , Jaime A. Bayan , Ashok S. Prabhu
IPC分类号： H01L23/495 , H05K1/11 , H01L21/82
CPC分类号： H01L23/49575 , H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L27/0688 , H01L27/088 , H01L2224/05554 , H01L2224/40091 , H01L2224/40095 , H01L2224/40245 , H01L2224/48247 , H01L2224/49109 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/07802 , H01L2924/1306 , H01L2924/181 , H05K1/0296 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.
摘要翻译：描述了用于实现小尺寸功率转换器和小尺寸功率转换器装置的有效制造的方法和系统。

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