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31. 发明授权

US07064978B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07064978B2
公开(公告)日：2006-06-20
申请号：US10351180
申请日：2003-01-24
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

32. 发明授权

US6009022A Node-precise voltage regulation for a MOS memory system 有权
标题翻译：用于MOS存储器系统的节点精确电压调节
公开(公告)号：US6009022A
公开(公告)日：1999-12-28
申请号：US189109
申请日：1998-11-09
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C16/30 , G11C7/00
CPC分类号： G11C7/12 , G11C16/30 , G11C5/147 , G11C8/08
摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.
摘要翻译：片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压。位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较差分输出比较器。用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

33. 发明授权

US5835420A Node-precise voltage regulation for a MOS memory system 失效
标题翻译：用于MOS存储器系统的节点精确电压调节
公开(公告)号：US5835420A
公开(公告)日：1998-11-10
申请号：US884251
申请日：1997-06-27
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C16/30 , G11C7/00
CPC分类号： G11C7/12 , G11C16/30 , G11C5/147 , G11C8/08
摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from at least one of which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.
摘要翻译：片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压中的至少一个。位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较差分输出比较器。用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

34. 发明授权

US5682350A Flash memory with divided bitline 失效
标题翻译：闪存分频线
公开(公告)号：US5682350A
公开(公告)日：1997-10-28
申请号：US726670
申请日：1996-10-07
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines, the drains of flash transistors in each column are coupled to common metal 1 lines divided into even metal 1 lines and odd metal 1 lines and the sources of the flash transistors are coupled to a common sourceline. A set of first selection transistors are coupled between even metal 1 lines and metal 2 lines having a pitch twice that of said metal 1 lines and controlled by a first select signal to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistors are coupled between odd metal 1 lines and the metal 2 lines and controlled by a second select signal to selectively couple the odd metal 1 lines to the metal 2 lines. In one embodiment, the set of first selection transistors and the set of second selection transistors are large in comparison to the flash transistors. Advantages of the invention include improved selection of memory cells, higher memory cell density and lower resistance in the memory cell selection circuitry.
摘要翻译：闪速存储器包括形成多行和多列的闪存晶体管组，每个闪存晶体管具有栅极，漏极和源极，其中每行中的闪存晶体管的栅极耦合到公共字线，闪存的漏极每列中的晶体管耦合到分为偶数金属1线和奇数金属1线的公共金属1线，并且闪存晶体管的源耦合到公共源极线。一组第一选择晶体管耦合在偶数金属1线和金属2线之间，金属2线具有两倍于所述金属1线的间距，并由第一选择信号控制，以选择性地将偶数金属1线耦合到金属2线。一组第二选择晶体管耦合在奇数金属1线和金属2线之间，并由第二选择信号控制，以将奇数金属1线选择性地耦合到金属2线。在一个实施例中，与闪存晶体管相比，该组第一选择晶体管和该组第二选择晶体管较大。本发明的优点包括存储器单元的改进选择，更高的存储单元密度和较低的存储单元选择电路中的电阻。

35. 发明申请

US20110051524A1 Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device 失效
标题翻译：用于操作NAND类双电荷保持晶体管NOR闪存器件的方法和装置
公开(公告)号：US20110051524A1
公开(公告)日：2011-03-03
申请号：US12806848
申请日：2010-08-23
申请人： Fu-Chang Hsu , Peter W. Lee
发明人： Fu-Chang Hsu , Peter W. Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0458 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C16/3477 , G11C2211/5621
摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.
摘要翻译：用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

36. 发明授权

US07154783B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
标题翻译：组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作
公开(公告)号：US07154783B2
公开(公告)日：2006-12-26
申请号：US11011306
申请日：2004-12-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
摘要翻译：描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。闪存单元被块擦除时，EEPROM单元被字节擦除。小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

37. 发明授权

US07075826B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07075826B2
公开(公告)日：2006-07-11
申请号：US11036945
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/06
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

38. 发明授权

US06862223B1 MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT 有权
标题翻译：单声道，组合非易失性存储器允许使用统一的单元结构和技术与解码器和布局的新方案在单元格阵列中无干扰和分离的字节，页面和块写入
公开(公告)号：US06862223B1
公开(公告)日：2005-03-01
申请号：US10223208
申请日：2002-08-19
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

39. 发明授权

US06777292B2 Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
公开(公告)号：US06777292B2
公开(公告)日：2004-08-17
申请号：US10627183
申请日：2003-07-25
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
IPC分类号： H01L21336
CPC分类号： G11C16/3404 , G11C16/0416 , G11C16/344 , H01L27/115 , H01L29/66825
摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

40. 发明授权

US06757196B1 Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device 有权
标题翻译：两个晶体管闪存单元，用于具有可编程逻辑器件的EEPROM阵列
公开(公告)号：US06757196B1
公开(公告)日：2004-06-29
申请号：US10016898
申请日：2001-12-14
申请人： Hsing-Ya Tsao , Peter W. Lee , Fu-Chang Hsu
发明人： Hsing-Ya Tsao , Peter W. Lee , Fu-Chang Hsu
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , H01L27/115
摘要： The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage device and an NMOS transistor forming an access device. The floating gate transistor is programmed and erased using Fowler-Nordheim channel tunneling. The two transistor memory cell is used in a memory array of columns and rows where a column of cells is coupled by a bit line and a source line, and where a row of cells is coupled by a word line and an access line. The memory array is highly scalable and is targeted for low-voltage, high-speed and high-density programmable logic devices.
摘要翻译：本发明描述了具有对称的源极和漏极结构的双晶体管快速EEPROM存储单元，这允许单元大小不受编程和擦除操作的限制。存储单元包括形成非易失性存储器件的NMOS浮栅晶体管和形成存取器件的NMOS晶体管。使用Fowler-Nordheim通道隧道对浮栅晶体管进行编程和擦除。两个晶体管存储单元用于列和行的存储器阵列中，其中一列单元由位线和源极线耦合，并且其中一行单元通过字线和存取线耦合。内存阵列具有高度可扩展性，适用于低电压，高速和高密度可编程逻辑器件。

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