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    • 36. 发明授权
    • Capless low drop-out voltage regulator having discharge circuit compensating for on-chip output capacitance and response time
    • 具有放电电路补偿片上输出电容和响应时间的无限低压降稳压器
    • US08648578B2
    • 2014-02-11
    • US12679485
    • 2008-09-29
    • Hui ZhaoZhen Yang
    • Hui ZhaoZhen Yang
    • G05F1/613
    • G05F1/571
    • A voltage regulator is provided having one or more discharger circuits that compensate for low on-chip output capacitance and a slow loop response time. In one embodiment, the voltage regulator includes an output transistor coupled to an output voltage line, an output voltage sensing arrangement coupled to the output voltage line for producing an output feedback voltage, and an error amplifier coupled to the output feedback voltage, the output transistor, and a reference voltage for applying feedback control to the output transistor. A first discharger circuit is coupled to the output voltage line and to a reference potential, the first discharger circuit being triggered by a steep-rise overvoltage condition. In another embodiment, a combination of fast and slow discharger circuits is used to improve the load step response—i.e., to stop the output voltage from jumping too high and to pull it back to stable value very quickly, such that the load circuits are protected.
    • 提供了具有一个或多个放大器电路的电压调节器,其补偿片上输出电容的低电平和缓慢的环路响应时间。 在一个实施例中,电压调节器包括耦合到输出电压线的输出晶体管,耦合到输出电压线的输出电压感测装置,用于产生输出反馈电压,以及耦合到输出反馈电压的误差放大器,输出晶体管 以及用于向输出晶体管施加反馈控制的参考电压。 第一放电电路耦合到输出电压线和参考电位,第一放电电路由陡升过压状态触发。 在另一个实施例中,使用快速和慢速放电器电路的组合来改善负载阶跃响应 - 即停止输出电压跳跃太高并将其非常快地拉回稳定值,使得负载电路被保护 。
    • 37. 发明申请
    • Voltage Regulator Circuit
    • 稳压电路
    • US20130271094A1
    • 2013-10-17
    • US13808439
    • 2010-07-05
    • Amanda SunZhen YangKaihua Zheng
    • Amanda SunZhen YangKaihua Zheng
    • G05F1/625
    • G05F1/625G05F1/575
    • A voltage regulator circuit comprises an amplifier (10) having a first input coupled to a first reference voltage node; a power pass element (20) having a control terminal coupled to an output of the amplifier, an input coupled to a power supply input of the voltage regulator circuit, and an output coupled to an output of the voltage regulator circuit; a feedback circuit (30, 31) having an input coupled to the output of the power pass element and an output coupled to a second input of the amplifier; and a compensation module (60) comprising a transistor (61), wherein a gate or base terminal of the transistor is coupled to a second reference voltage node, a drain or collector terminal of the transistor is coupled to the output of the amplifier, and a source or emitter terminal of the transistor is coupled to the power supply input of the voltage regulator circuit. The voltage regulator circuit is capable to increase the power supply rejection ratio of low drop-out voltage regulators.
    • 电压调节器电路包括具有耦合到第一参考电压节点的第一输入的放大器(10) 功率通过元件(20),其具有耦合到所述放大器的输出端的控制端子,耦合到所述电压调节器电路的电源输入端的输入端和耦合到所述电压调节器电路的输出的输出; 反馈电路(30,31),其具有耦合到所述功率通过元件的输出的输入和耦合到所述放大器的第二输入的输出; 以及包括晶体管(61)的补偿模块(60),其中所述晶体管的栅极或基极端子耦合到第二参考电压节点,所述晶体管的漏极或集电极端子耦合到所述放大器的输出,以及 晶体管的源极或发射极端子耦合到电压调节器电路的电源输入端。 电压调节器电路能够提高低压差稳压器的电源抑制比。
    • 39. 发明授权
    • Electrically programmable device with embedded EEPROM and method for making thereof
    • 具有嵌入式EEPROM的电子可编程器件及其制造方法
    • US08354707B2
    • 2013-01-15
    • US12833939
    • 2010-07-09
    • Yi-Peng ChanSheng-He HuangZhen Yang
    • Yi-Peng ChanSheng-He HuangZhen Yang
    • H01L27/115
    • H01L27/11521H01L21/28273H01L27/11206H01L27/115H01L27/11519H01L27/11524H01L29/42324H01L29/7883
    • A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region.
    • 半导体器件包括衬底和覆盖衬底中的第一器件区域和第二器件区域的第一栅极氧化物层,第一器件区域中的第一栅极,以及第二器件区域中的第二栅极和第三栅极。 该装置还具有第一介电层,第一部分设置在第一栅极上,第二部分邻近第一栅极的侧壁设置,第三部分设置在第三栅极之上。 栅极间氧化物层设置在第一栅极上并且在第一介电层的第一部分和第二部分之间。 第四栅极覆盖在第一器件区域中的第二栅极氧化物层,栅极间氧化物层以及第一电介质层的第一部分和第二部分。 第五栅极覆盖设置在第二器件区域中的第三栅极上的第一电介质层的第三部分。
    • 40. 发明申请
    • ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF
    • 具有嵌入式EEPROM的电可编程器件及其制造方法
    • US20100276745A1
    • 2010-11-04
    • US12833939
    • 2010-07-09
    • YI-PENG CHANSheng-He HuangZhen Yang
    • YI-PENG CHANSheng-He HuangZhen Yang
    • H01L27/115H01L29/788
    • H01L27/11521H01L21/28273H01L27/11206H01L27/115H01L27/11519H01L27/11524H01L29/42324H01L29/7883
    • A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region.
    • 半导体器件包括衬底和覆盖衬底中的第一器件区域和第二器件区域的第一栅极氧化物层,第一器件区域中的第一栅极,以及第二器件区域中的第二栅极和第三栅极。 该装置还具有第一介电层,第一部分设置在第一栅极上,第二部分邻近第一栅极的侧壁设置,第三部分设置在第三栅极之上。 栅极间氧化物层设置在第一栅极上并且在第一介电层的第一部分和第二部分之间。 第四栅极覆盖在第一器件区域中的第二栅极氧化物层,栅极间氧化物层以及第一电介质层的第一部分和第二部分。 第五栅极覆盖设置在第二器件区域中的第三栅极上的第一电介质层的第三部分。