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31. 发明授权

US07213133B2 Method and apparatus for avoiding write-after-write hazards in an execute-ahead processor 有权
标题翻译：用于在执行前处理器中避免写后危害的方法和装置
公开(公告)号：US07213133B2
公开(公告)日：2007-05-01
申请号：US10923217
申请日：2004-08-20
申请人： Paul Caprioli , Shailender Chaudhry
发明人： Paul Caprioli , Shailender Chaudhry
IPC分类号： G06F9/30
CPC分类号： G06F9/3863 , G06F9/30181 , G06F9/30189 , G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3857
摘要： One embodiment of the present invention provides a system that avoids write-after-write (WAW) hazards while speculatively executing instructions. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode. During this execute-ahead mode, instructions that cannot be executed because of unresolved data dependencies are deferred, and other non-deferred instructions are executed in program order. If an unresolved data dependency is resolved during the execute-ahead mode, the system moves into a deferred mode wherein the system executes deferred instructions. While executing a deferred instruction, if dependency information for an associated destination register indicates that a WAW hazard potentially exists with a following non-deferred instruction, the system executes the deferred instruction to produce a result, and forwards the result to be used by subsequent instructions in a pipeline and/or deferred queue for the processor. The system does so without committing the result to the architectural state of the destination register. In this way, the system makes the result available to the subsequent instructions without overwriting a result produced by the following non-deferred instruction, thereby avoiding a WAW hazard.
摘要翻译：本发明的一个实施例提供了一种在推测性地执行指令时避免写后写入（WAW）危险的系统。系统以正常执行模式启动，其中系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，系统产生检查点，延迟指令，并以执行方式执行后续指令。在此执行模式期间，由于未解决的数据依赖关系而无法执行的指令被延迟，并且其他非延迟指令以程序顺序执行。如果在执行提前模式期间解决了未解决的数据依赖关系，则系统进入延迟模式，其中系统执行延迟指令。在执行延迟指令时，如果相关联的目标寄存器的依赖关系信息指示可能存在具有以下非延迟指令的WAW危险，则系统执行延迟指令以产生结果，并转发后续指令使用的结果在处理器的流水线和/或延迟队列中。系统没有将结果提交到目标寄存器的架构状态。以这种方式，系统使结果可用于随后的指令，而不会覆盖由以下非延迟指令产生的结果，从而避免WAW危险。

32. 发明申请

US20060242365A1 Method and apparatus for suppressing duplicative prefetches for branch target cache lines 有权
标题翻译：用于抑制分支目标缓存行的重复预取的方法和装置
公开(公告)号：US20060242365A1
公开(公告)日：2006-10-26
申请号：US11111654
申请日：2005-04-20
申请人： Abid Ali , Paul Caprioli , Shailender Chaudhry , Miles Lee
发明人： Abid Ali , Paul Caprioli , Shailender Chaudhry , Miles Lee
IPC分类号： G06F13/00
CPC分类号： G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F12/0862
摘要： A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fetch buffer. If a control transfer instruction in the first cache line has a target instruction which is located in the second cache line, the system determines if the control transfer instruction is also located at the end of the first cache line so that a corresponding delay slot for the control transfer instruction is located at the beginning of the second cache line. If so, the system suppresses a subsequent prefetch for a target cache line containing the target instruction because the target instruction is located in the second cache line which has already been prefetched.
摘要翻译：一种抑制分支目标缓存行重复预取的系统。在操作期间，系统将第一个高速缓存行提取到获取缓冲区中。系统然后将紧跟在第一个高速缓存行之后的第二个高速缓存行预取到获取缓冲区。如果第一高速缓存行中的控制传送指令具有位于第二高速缓存行中的目标指令，则系统确定控制传输指令是否也位于第一高速缓存行的末端，使得对应的延迟时隙控制传输指令位于第二高速缓存行的开头。如果是这样，则由于目标指令位于已经被预取的第二高速缓存行中，所以系统抑制对包含目标指令的目标高速缓存行的后续预取。

33. 发明申请

US20050273583A1 Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor 有权
标题翻译：在执行处理器中执行膜指令语义的方法和装置
公开(公告)号：US20050273583A1
公开(公告)日：2005-12-08
申请号：US11083263
申请日：2005-03-16
申请人： Paul Caprioli , Shailender Chaudhry , Marc Tremblay
发明人： Paul Caprioli , Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38 , G06F9/45 , G06F12/08
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857
摘要： One embodiment of the present invention provides a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued. During operation in a normal-execution mode, the processor issues instructions for execution in program order. Upon encountering a membar instruction, the processor determines if the load buffer and store buffer contain unresolved loads and stores. If so, the processor defers the membar instruction and executes subsequent program instructions in execute-ahead mode. In execute-ahead mode, instructions that cannot be executed because of an unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. When all stores and loads that precede the membar instruction have been committed to memory from the store buffer and the load buffer, the processor enters a deferred mode and executes the deferred instructions, including the membar instruction, in program order. If all deferred instructions have been executed, the processor returns to the normal-execution mode and resumes execution from the point where the execute-ahead mode left off.
摘要翻译：本发明的一个实施例提供了一种便于在执行前处理器中执行存储器屏障（membar）指令的系统，其中，在允许执行后续指令之前，该指令强制缓冲的负载和存储完成。在正常执行模式下的操作期间，处理器以程序顺序发出执行指令。在遇到一条指令时，处理器确定加载缓冲区和存储缓冲区是否包含未解决的负载和存储。如果是这样，则处理器延迟膜指令，并以执行模式执行后续的程序指令。在执行提前模式下，由于未解决的数据依赖关系而无法执行的指令被延迟，并且其他非延迟指令以程序顺序执行。当存储缓冲区和加载缓冲区之前的所有存储和负载已经提交到存储缓冲区的内存中时，处理器以程序顺序进入延迟模式并执行延迟指令，包括指令指令。如果所有延迟指令都已执行，则处理器返回到正常执行模式，并从执行方式退出的点恢复执行。

34. 发明申请

US20050257034A1 Branch target aware instruction prefetching technique 有权
标题翻译：分支目标感知指令预取技术
公开(公告)号：US20050257034A1
公开(公告)日：2005-11-17
申请号：US10996027
申请日：2004-11-23
申请人： Paul Caprioli , Shailender Chaudhry
发明人： Paul Caprioli , Shailender Chaudhry
IPC分类号： G06F9/32 , G06F9/38 , G06F9/44
CPC分类号： G06F9/3804 , G06F9/382 , G06F9/3844 , G06F9/3846
摘要： Inspecting a currently fetched instruction group and determining branching behavior of the currently fetched instruction group, allows for intelligent instruction prefetching. A currently fetched instruction group is predecoded and, assuming the currently fetch instruction group includes a branch type instruction, a branch target is characterized in relation to a fetch boundary, which delimits a memory region contiguous with the memory region that hosts the currently fetched instruction group. Instruction prefetching is included based, at least in part, on the predecoded characterization of the branch target.
摘要翻译：检查当前获取的指令组并确定当前获取的指令组的分支行为，允许智能指令预取。当前获取的指令组被预解码，并且假设当前获取指令组包括分支类型指令，则分支目标与获取边界相关，其限定与承载当前获取的指令组的存储器区域相邻的存储器区域。基于至少部分地基于分支目标的预解码特征来包括指令预取。

35. 发明授权

US08151084B2 Using address and non-address information for improved index generation for cache memories 有权
标题翻译：使用地址和非地址信息来改进高速缓存存储器的索引生成
公开(公告)号：US08151084B2
公开(公告)日：2012-04-03
申请号：US12018407
申请日：2008-01-23
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F12/10
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译：本发明的实施例提供一种生成高速缓冲存储器的索引的系统。系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。然后系统获得与请求相关联的非地址信息。接下来，系统使用地址信息和非地址信息来生成索引。然后，系统使用索引来实现对高速缓存的访问。

36. 发明授权

US07484080B2 Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer 有权
标题翻译：在执行超前模式期间遇到的存储进入侦察模式超过存储缓冲区的容量
公开(公告)号：US07484080B2
公开(公告)日：2009-01-27
申请号：US11103912
申请日：2005-04-11
申请人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
发明人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
IPC分类号： G06F9/00
CPC分类号： G06F9/3863 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3865
摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store. If the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.
摘要翻译：本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。在正常执行模式下，系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。如果在执行超前模式期间遇到的存储的数量超过了存储缓冲区的容量，这意味着由于存储缓冲区被选通，在执行提前模式下，存储缓冲区将永远不会有额外的空间来接受附加存储，系统直接进入侦察模式，无需等待延期队列最终填满。

37. 发明授权

US07478203B2 Technique for eliminating dead stores in a processor 有权
标题翻译：消除处理器中死区的技术
公开(公告)号：US07478203B2
公开(公告)日：2009-01-13
申请号：US11371144
申请日：2006-03-08
申请人： Paul Caprioli , Shailender Chaudhry
发明人： Paul Caprioli , Shailender Chaudhry
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1064
摘要： A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the on-chip store. The technique determines whether new data bytes of the new data and associated old data bytes of the old data are different. The new data bytes are then written to the on-chip store. When updating an off-chip store, only the new data bytes that are different are written to the off-chip store. In this manner, off-chip bandwidth requirements for a processor may be reduced.
摘要翻译：用于减少处理器的片外带宽要求的技术从处理器的片上存储器中的位置读取旧数据，以准备将新数据写入片上存储器中的位置。该技术确定新数据的新数据字节和旧数据的相关旧数据字节是否不同。然后将新的数据字节写入片上存储。更新片外存储时，仅将不同的新数据字节写入片外存储。以这种方式，可以减少处理器的片外带宽需求。

38. 发明申请

US20080189531A1 Preventing register data flow hazards in an SST processor 有权
标题翻译：防止SST处理器中的寄存器数据流危害
公开(公告)号：US20080189531A1
公开(公告)日：2008-08-07
申请号：US11703462
申请日：2007-02-06
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/44
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863
摘要： One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode using a first thread. While executing instructions in the execute-ahead mode, the system maintains dependency information for each register indicating whether the register is subject to an unresolved data dependency. Upon the resolution of a data dependency during execute-ahead mode, the system copies dependency information to a speculative copy of the dependency information. The system then commences execution of the deferred instructions in a deferred mode using a second thread. While executing instructions in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a write-after-write (WAW) hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the system uses the second thread to execute the deferred instruction to produce a result and forwards the result to be used by subsequent deferred instructions without committing the result to the architectural state of the destination register. Hence, the system makes the result available to the subsequent deferred instructions without overwriting the result produced by a following non-deferred instruction.
摘要翻译：本发明的一个实施例提供一种在同时推测的线程中防止数据危害的系统。系统通过使用第一个线程以执行模式执行指令来启动。在执行执行模式下执行指令时，系统维护每个寄存器的依赖信息，指示寄存器是否受到未解析的数据依赖。在执行提前模式下解析数据依赖关系时，系统将依赖关系信息复制到依赖关系信息的推测性副本。然后，系统使用第二个线程以延迟模式开始执行延迟指令。在延迟模式下执行指令时，如果目的寄存器的依赖关系信息的推测性副本指示在执行提前模式下由第一线程执行的后续非延迟指令存在写后写入（WAW）危险，系统使用第二个线程执行延迟指令以产生结果，并转发后续延迟指令使用的结果，而不将结果提交到目标寄存器的体系结构状态。因此，系统使结果可用于后续延期指令，而不会覆盖由以下非延迟指令产生的结果。

39. 发明授权

US07353363B2 Patchable and/or programmable decode using predecode selection 有权
标题翻译：使用预先代码选择进行补丁和/或可编程解码
公开(公告)号：US07353363B2
公开(公告)日：2008-04-01
申请号：US11277716
申请日：2006-03-28
申请人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/30196 , G06F9/328 , G06F9/382 , G06F9/3857 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, between fixed decode and programmable decode paths provided by a processor. In this way, a patchable and/or programmable decode mechanism can be efficiently provided. In some realizations, either (or both) predecode or (and) decode may be configured or reconfigured post-manufacture. In some realizations, either (or both) predecode or (and) decode may be configured at (or about) initialization. In some realizations, either (or both) predecode or (and) decode may be configured at run-time.
摘要翻译：已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。特别地，已经发现，可以采用可配置的预解码机制来针对相应的指令模式在由处理器提供的固定解码和可编程解码路径之间进行选择。以这种方式，可以有效地提供可修补和/或可编程的解码机制。在一些实现中，可以在制造后配置或重新配置（或两者）预解码或（和）解码。在某些实现中，可以在（或约）初始化时配置（或两者）预解码或（和）解码。在某些实现中，可以在运行时配置（或两者）预解码或（和）解码。

40. 发明申请

US20070226472A1 Method and apparatus for sampling instructions on a processor that supports speculative execution 有权
标题翻译：用于在支持推测性执行的处理器上对指令进行采样的方法和装置
公开(公告)号：US20070226472A1
公开(公告)日：2007-09-27
申请号：US11405965
申请日：2006-04-17
申请人： Shailender Chaudhry , Paul Caprioli , Sherman Yip
发明人： Shailender Chaudhry , Paul Caprioli , Sherman Yip
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F9/3842 , G06F9/3867
摘要： One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器上对指令进行采样的系统。系统首先选择指令，其中选择指令涉及选择从指令获取单元或延迟队列接收的指令，其中延迟队列保存由于未解决的数据依赖性而延迟的延迟指令。然后，系统在执行所选择的指令期间记录关于所选指令的信息，由此所记录的信息可用于确定处理器的性能

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