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31. 发明申请

US20060143373A1 Processor having content addressable memory for block-based queue structures 有权
标题翻译：具有内容可寻址存储器的处理器，用于基于块的队列结构
公开(公告)号：US20060143373A1
公开(公告)日：2006-06-29
申请号：US11027601
申请日：2004-12-28
申请人： Sanjeev Jain , Gilbert Wolrich , Debra Bernstein
发明人： Sanjeev Jain , Gilbert Wolrich , Debra Bernstein
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L45/7453 , H04L49/90
摘要： Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.
摘要翻译：排队命令信息存储在内容可寻址存储器（CAM）中，其中接收到用于第一队列的排队命令，检查CAM以确定是否存在用于第一队列的命令，并且如果发现第一队列的命令是在多个CAM条目中，信息被存储在所接收的命令的链表中。

32. 发明申请

US20060140203A1 System and method for packet queuing 审中-公开
标题翻译：分组排队的系统和方法
公开(公告)号：US20060140203A1
公开(公告)日：2006-06-29
申请号：US11026313
申请日：2004-12-28
申请人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein
发明人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein
IPC分类号： H04L12/28
CPC分类号： H04L49/90
摘要： Data is enqueued and dequeued using a block-based queuing structure.
摘要翻译：数据排队并使用基于块的排队结构出队。

33. 发明申请

US20060140192A1 Flexible mesh structure for hierarchical scheduling 有权
标题翻译：灵活的网格结构，用于分层调度
公开(公告)号：US20060140192A1
公开(公告)日：2006-06-29
申请号：US11024957
申请日：2004-12-29
申请人： Sanjeev Jain , Gilbert Wolrich
发明人： Sanjeev Jain , Gilbert Wolrich
IPC分类号： H04J3/14 , H04J1/16 , H04L1/00 , H04L12/26 , H04L12/56 , H04L12/28
CPC分类号： H04L47/24 , H04L47/50
摘要： Systems and methods employing a flexible mesh structure for hierarchical scheduling are disclosed. The method generally includes reading a packet grouping configured in a two dimensional mesh structure of N columns, each containing M packets, selecting and promoting a column best packet from each column to a final row containing N packets, reading, selecting and promoting a final best packet from the final row to a next level in the hierarchy. Each time a final best packet is selected and promoted, the mesh structure can be refreshed by replacing the packet corresponding to the final best packet, and reading, selecting and promoting a column best packet from the column containing the replacement packet to the final row. As only the column containing the replacement packet and the final row are read and compared for each refresh, the mesh structure results in reduced read and compare cycles for schedule determination.
摘要翻译：公开了采用柔性网格结构进行分层调度的系统和方法。该方法通常包括读取以N列的二维网格结构配置的分组分组，每个分组包含M个分组，从每列选择并提升列最佳分组到包含N个分组的最后一行，读取，选择和促进最终最佳分组从最后一行到层次结构中的下一个级别。每次选择和提升最终最佳分组时，可以通过替换与最终最佳分组相对应的分组来刷新网格结构，并从包含替换分组的列到最后一行读取，选择和促进列最佳分组。由于只有包含替换数据包和最后一行的列被读取并进行比较才能进行每次刷新，所以网格结构导致读取和比较周期减少以用于计划确定。

34. 发明申请

US20060095730A1 Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses 审中-公开
标题翻译：通过使用交错的程序地址共享相邻的控制存储来扩展计算引擎代码空间
公开(公告)号：US20060095730A1
公开(公告)日：2006-05-04
申请号：US10955643
申请日：2004-09-30
申请人： Gilbert Wolrich , Mark Rosenbluth , Matthew Adiletta , Hugh Wilkinson , Jose Niell , Rajagopal Narayanan , Sanjeev Jain
发明人： Gilbert Wolrich , Mark Rosenbluth , Matthew Adiletta , Hugh Wilkinson , Jose Niell , Rajagopal Narayanan , Sanjeev Jain
IPC分类号： G06F9/30
CPC分类号： G06F12/0607 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.
摘要翻译：通过使用交错寻址方案共享相邻控制存储器来支持计算引擎代码空间的扩展的方法和装置。与原始指令线程相对应的指令被划分为存储在相应控制存储器中的多个交错序列。在线程执行期间，基于交织方案以重复的顺序从控制存储器检索指令。例如，在一个实施例中，两个计算引擎共享两个控制存储。因此，给定线程的指令以交替方式从控制存储器顺序加载。在另一个实施例中，四个控制存储由四个计算引擎共享。在这种情况下，线程中的指令使用四个存储进行交织，并且每个存储在代码序列中每第四个指令被访问。还提供了处理分支操作以维持对控制存储的同步访问的方案。

35. 发明申请

US20060069854A1 Method and apparatus providing efficient queue descriptor memory access 有权
标题翻译：提供有效的队列描述符存储器访问的方法和装置
公开(公告)号：US20060069854A1
公开(公告)日：2006-03-30
申请号：US10955969
申请日：2004-09-30
申请人： Sanjeev Jain , Gilbert Wolrich
发明人： Sanjeev Jain , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： G06F12/121
摘要： A system having queue control structures includes a conflict avoidance mechanism to prevent memory bank conflicts for queue descriptor access. In one embodiment, a queue descriptor bank table contains information including in which memory bank each queue descriptor is stored.
摘要翻译：具有队列控制结构的系统包括冲突避免机制，以防止存储器组冲突用于队列描述符访问。在一个实施例中，队列描述符库表包含包含存储每个队列描述符的存储体的信息。

36. 发明申请

US20050025055A1 Network statistics 有权
标题翻译：网络统计
公开(公告)号：US20050025055A1
公开(公告)日：2005-02-03
申请号：US10628997
申请日：2003-07-28
申请人： Sanjeev Jain , Donald Hooper
发明人： Sanjeev Jain , Donald Hooper
IPC分类号： H04L1/00 , H04L12/26
CPC分类号： H04L43/00
摘要： In general, in one aspect, the disclosure describes a method of tracking a network statistic stored within a collection of bits. The method includes storing the collection of bits storing the network statistic as at least a first portion and a second portion. The first portion includes a set of least-significant bits and the second portion includes a set of more significant bits. The method also includes incrementing the first portion based on a packet and=determining if the incrementing of the first portion caused a designated bit of the first portion to be set. If it is determined that the incrementing of the first portion caused the designated bit to be set, the method increments the value stored by the second portion and resets the designated bit within the first portion.
摘要翻译：一般来说，一方面，本公开描述了一种跟踪存储在位集合内的网络统计量的方法。该方法包括将存储网络统计量的位的集合存储为至少第一部分和第二部分。第一部分包括一组最低有效位，并且第二部分包括一组更有效位。该方法还包括基于分组递增第一部分，以及确定第一部分的递增是否导致要设置的第一部分的指定位。如果确定第一部分的增加导致指定的位被设置，则该方法增加由第二部分存储的值，并且使第一部分内的指定位复位。

37. 发明授权

US4972711A Isometric lifting device 失效
标题翻译：等轴提升装置
公开(公告)号：US4972711A
公开(公告)日：1990-11-27
申请号：US160758
申请日：1988-02-26
申请人： Sanjeev Jain , John E. Vermette
发明人： Sanjeev Jain , John E. Vermette
IPC分类号： A61B5/22 , A63B24/00
CPC分类号： A63B21/0023 , A61B5/224 , A63B2220/54 , A63B2225/093 , Y10S482/90
摘要： A device for measuring linear force which is converted to rotational force or torque. Initially, force is applied in a linear direction to a means for transmitting that force to a rotatable shaft where it is converted to rotational force which can be measured by a strain gauge. The device is mounted on a vertically adjustable column attached to a moveable base.
摘要翻译：用于测量线性力的装置，其被转换成旋转力或扭矩。最初，向直线方向施加力以将该力传递到可旋转轴的装置，在那里将其转换成可由应变计测量的旋转力。该装置安装在可移动基座上的可垂直调节的柱上。

38. 发明授权

US08370274B2 Apparatuses and methods for deterministic pattern matching 失效
标题翻译：确定性模式匹配的设备和方法
公开(公告)号：US08370274B2
公开(公告)日：2013-02-05
申请号：US12475357
申请日：2009-05-29
申请人： David K. Cassetti , Sanjeev Jain , Christopher F. Clark , Lokpraveen Bhupathy Mosur
发明人： David K. Cassetti , Sanjeev Jain , Christopher F. Clark , Lokpraveen Bhupathy Mosur
IPC分类号： G06F13/00 , G06F7/02
CPC分类号： G06F7/02 , G06F2207/025
摘要： Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.
摘要翻译：提出了执行模式匹配的设备和方法。在一个实施例中，一种设备包括存储器，用于存储第一模式表，其包括指示输入数据的字节是否匹配模式的信息，以及是否忽略在输入数据的剩余字节中发生的模式的其他匹配。该装置还包括耦合到存储器的一字节匹配逻辑，以便基于第一模式表中的信息来确定相对于输入数据的一个字节的匹配事件。该装置还包括控制单元，用于基于第一模式表的信息来过滤模式的其他匹配。

39. 发明申请

US20110145205A1 Packet Boundary Spanning Pattern Matching Based At Least In Part Upon History Information 审中-公开
标题翻译：基于历史信息的分组边界跨度模式匹配最小化
公开(公告)号：US20110145205A1
公开(公告)日：2011-06-16
申请号：US12637488
申请日：2009-12-14
申请人： Sanjeev Jain , Christopher F. Clark , David K. Cassetti
发明人： Sanjeev Jain , Christopher F. Clark , David K. Cassetti
IPC分类号： G06F17/30 , G06F15/16 , G06F21/00
CPC分类号： H04L63/1416 , G06F21/552 , H04L63/123
摘要： An embodiment may include circuitry to determine, at least in part, based at least in part upon history information, whether one or more reference patterns are present in a data stream in a packet flow. The data stream may span at least one packet boundary in the packet flow. The history information may include a beginning portion of a packet in the data stream, an ending portion of the packet, and another portion of the data stream. The circuitry may overwrite the another portion of the history information with a respective portion of the data stream to be examined by the circuitry depending, at least in part, upon whether the circuitry determines, at least in part, whether the one or more reference patterns are present in the data stream. The respective portion may be relatively closer than the another portion is to a beginning of the data stream.
摘要翻译：一个实施例可以包括至少部分地至少部分地基于历史信息来确定在分组流中的数据流中是否存在一个或多个参考模式的电路。数据流可以跨越分组流中的至少一个分组边界。历史信息可以包括数据流中的分组的开始部分，分组的结束部分和数据流的另一部分。至少部分地，至少部分地确定电路是否确定一个或多个参考模式，电路可以覆盖由电路检查的数据流的相应部分的另一部分的历史信息存在于数据流中。相应的部分可以比另一部分相对更靠近数据流的开头。

40. 发明授权

US07853951B2 Lock sequencing to reorder and grant lock requests from multiple program threads 有权
标题翻译：锁定顺序以重新排序并从多个程序线程授予锁定请求
公开(公告)号：US07853951B2
公开(公告)日：2010-12-14
申请号：US11190112
申请日：2005-07-25
申请人： Mark Rosenbluth , Sanjeev Jain , Gilbert Wolrich
发明人： Mark Rosenbluth , Sanjeev Jain , Gilbert Wolrich
IPC分类号： G06F9/46 , G06F13/00 , G06F7/00
CPC分类号： G06F9/52
摘要： In general, in one aspect, the disclosure describes a processor that includes multiple multi-threaded programmable units integrated on a single die. The die also includes circuitry communicatively coupled to the programmable units that reorders and grants lock requests received from the threads based on an order in which the threads requested insertion into a sequence of lock grants.
摘要翻译：通常，在一个方面，本公开描述了一种处理器，其包括集成在单个管芯上的多个多线程可编程单元。芯片还包括通信地耦合到可编程单元的电路，其基于线程请求插入到锁定授权序列中的顺序重新排序和授予从线程接收到的锁定请求。

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