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31. 发明授权

US08909835B2 Computer system and method of controlling computer system 有权
标题翻译：计算机系统及其控制方法
公开(公告)号：US08909835B2
公开(公告)日：2014-12-09
申请号：US12779456
申请日：2010-05-13
申请人： Masaki Kataoka , Hideaki Komatsu
发明人： Masaki Kataoka , Hideaki Komatsu
IPC分类号： G06F13/14 , G06F13/24
CPC分类号： G06F13/24
摘要： CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction.
摘要翻译： CPU架构被修改，使得可以基于CPU的指令解码器的解码结果直接改变中断屏蔽寄存器的内容。这种修改在改变CPU设计时不需要大量的人力。此外，扩展的CALL指令和扩展软件中断指令被添加到CPU，并且扩展CALL指令和扩展软件中断指令中的每一个还具有改变中断屏蔽寄存器的值的功能。原子性通过以下方式实现：允许这样一个指令同时执行一个进程的调用和中断屏蔽寄存器的值改变; 并在执行单个指令期间禁用其他中断。

32. 发明授权

US08671399B2 Systems and methods for efficiently using stack registers and storage medium therefor 失效
标题翻译：有效利用堆栈寄存器和存储介质的系统和方法
公开(公告)号：US08671399B2
公开(公告)日：2014-03-11
申请号：US11931300
申请日：2007-10-31
申请人： Akira Koseki , Mikio Takeuchi , Hideaki Komatsu
发明人： Akira Koseki , Mikio Takeuchi , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/447 , G06F8/441 , G06F8/443
摘要： A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled. The register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.
摘要翻译：编译器包括用于分配用于要编译的程序中的指令的寄存器的寄存器分配器，以及用于根据由寄存器分配器执行的寄存器分配结果来生成目标代码的代码生成器。寄存器分配器为要编译的程序中的指令分配逻辑寄存器。寄存器分配进一步向物理寄存器分配分配给程序指令的逻辑寄存器，使得在编译程序中的过程调用中存在的物理寄存器从寄存器堆栈的底部分配。

33. 发明申请

US20140025365A1 SIMULATION METHOD, SYSTEM, AND PROGRAM 有权
标题翻译：模拟方法，系统和程序
公开(公告)号：US20140025365A1
公开(公告)日：2014-01-23
申请号：US13555731
申请日：2012-07-23
申请人： Kohichi Kajitani , Hideaki Komatsu , Shu Shimizu
发明人： Kohichi Kajitani , Hideaki Komatsu , Shu Shimizu
IPC分类号： G06F9/455
CPC分类号： G06F17/5095 , B60T8/4081 , G06F11/3632 , G06F17/5009 , G06F2217/86
摘要： System and method for achieving reproducibility of a simulation operation while reasonably keeping an operation speed. A peripheral scheduler clears completion flags of all the peripheral emulators to thereby start parallel operations thereof. Then, based on processing break timing set for the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of processor emulators and plant simulators up until a time point of the time T. The peripheral scheduler waits for setting of a completion flag of the peripheral P. In response to the setting, the peripheral scheduler performs data synchronization among the peripheral P, the processor emulators, and the plant simulators.
摘要翻译：在合理保持操作速度的同时实现模拟操作的再现性的系统和方法。外设调度器清除所有外围仿真器的完成标志，从而开始其并行操作。然后，基于针对各个外围仿真器设置的处理中断定时，外围调度器发现最早计划到达处理中断的外围仿真器之一。所寻找的外设仿真器被称为外设P.在外设P的处理中断的时间为T的情况下，外围调度器继续执行处理器仿真器和工厂模拟器直到时间T的时间点。外设调度器等待设置外设P的完成标志。响应于该设置，外围调度器在外设P，处理器模拟器和工厂模拟器之间执行数据同步。

34. 发明授权

US08412496B2 Simulation system, method, and program 失效
标题翻译：仿真系统，方法和程序
公开(公告)号：US08412496B2
公开(公告)日：2013-04-02
申请号：US12791096
申请日：2010-06-01
申请人： Arquimedes Martinez Canedo , Hideaki Komatsu
发明人： Arquimedes Martinez Canedo , Hideaki Komatsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5095
摘要： A system, method and program to improve the processing speed of a simulation system. A processing system finds an entry point so that functional blocks cover a broad range. The processing system places code of a look-ahead dispatcher for assigning processing. The look-ahead dispatcher monitors an input state at the entry point to determine whether the input state is a stable state. If the input state is stable, the look-ahead dispatcher calls an adaptive execution module at some frequency or otherwise calls an idle execution module. The adaptive execution module performs processing on multiple timestamps at once. When a discrete system receives an input event, the look-ahead dispatcher calls a recovery execution module. Based on the input event on that occasion, the timestamp, and a value stored in a state vector, the recovery execution module calculates a state for which recovery is performed.
摘要翻译：一种提高仿真系统处理速度的系统，方法和程序。处理系统找到入口点，使得功能块覆盖广泛的范围。处理系统放置用于分配处理的预先调度器的代码。先行调度器监视入口点处的输入状态，以确定输入状态是否为稳定状态。如果输入状态稳定，则预先调度器以某种频率调用自适应执行模块，或以其他方式调用空闲执行模块。自适应执行模块一次执行多个时间戳的处理。当离散系统接收到输入事件时，预先调度器调用恢复执行模块。基于当时的输入事件，时间戳和存储在状态向量中的值，恢复执行模块计算执行恢复的状态。

35. 发明授权

US08407679B2 Source code processing method, system and program 有权
标题翻译：源代码处理方法，系统和程序
公开(公告)号：US08407679B2
公开(公告)日：2013-03-26
申请号：US12603598
申请日：2009-10-22
申请人： Hideaki Komatsu , Takeo Yoshizawa
发明人： Hideaki Komatsu , Takeo Yoshizawa
IPC分类号： G06F9/45
CPC分类号： G06F8/70 , G06F8/45 , G06F8/456
摘要： A method, system, and computer readable article of manufacture to enable parallel execution of a divided source code in a multiprocessor system. The method includes the steps of: inputting an original source code by an input device into the computing apparatus; finding a critical path in the original source code by a critical path cut module; cutting the critical path in the original source code into a plurality of process block groups by the critical path cut module; and dividing the plurality of process block groups among a plurality of processors in the multiprocessor system by a CPU assignment code generation module to produce the divided source code. The system includes an input device; a critical path cut module; and a CPU assignment code generation unit to produce the divided source code. The computer readable article of manufacture includes instructions to implement the method.
摘要翻译：一种方法，系统和计算机可读制品，用于在多处理器系统中并行执行分割的源代码。该方法包括以下步骤：通过输入装置将原始源代码输入到计算装置中; 通过关键路径切割模块找到原始源代码中的关键路径; 通过关键路径切割模块将原始源代码中的关键路径切割成多个进程块组; 以及通过CPU分配码产生模块在多处理器系统中的多个处理器之间划分多个处理块组，以产生分割的源代码。该系统包括输入装置; 关键路径切割模块; 以及CPU分配代码生成单元，用于产生分割的源代码。计算机可读制品包括实现该方法的指令。

36. 发明申请

US20110131554A1 APPLICATION GENERATION SYSTEM, METHOD, AND PROGRAM PRODUCT 审中-公开
标题翻译：应用生成系统，方法和程序产品
公开(公告)号：US20110131554A1
公开(公告)日：2011-06-02
申请号：US12955147
申请日：2010-11-29
申请人： Munehiro Doi , Hideaki Komatsu , Kumiko Maeda , Masana Murase , Takeo Yoshizawa
发明人： Munehiro Doi , Hideaki Komatsu , Kumiko Maeda , Masana Murase , Takeo Yoshizawa
IPC分类号： G06F9/44
CPC分类号： G06F8/4441
摘要： A method, system and computer program product for optimizing performance of an application running on a hybrid system. The method includes the steps of: selecting a first user defined operator from a library component within the application; determining at least one available hardware resource; generating at least one execution pattern for the first user defined operator based on the available hardware resource; compiling the execution pattern; measuring the execution speed of the execution pattern on the available hardware resource; and storing the execution speed and the execution pattern in an optimization table; where at least one of the steps is carried out using a computer device so that performance of said application is optimized on the hybrid system.
摘要翻译：一种用于优化在混合系统上运行的应用的性能的方法，系统和计算机程序产品。该方法包括以下步骤：从应用程序内的库组件中选择第一用户定义的运算符; 确定至少一个可用硬件资源; 基于所述可用硬件资源为所述第一用户定义的运算符生成至少一个执行模式; 编译执行模式; 测量可用硬件资源上执行模式的执行速度; 并将执行速度和执行模式存储在优化表中; 其中使用计算机设备执行至少一个步骤，使得在混合系统上优化所述应用的性能。

37. 发明申请

US20110107162A1 PARALLELIZATION METHOD, SYSTEM AND PROGRAM 失效
标题翻译：并行化方法，系统与程序
公开(公告)号：US20110107162A1
公开(公告)日：2011-05-05
申请号：US12913822
申请日：2010-10-28
申请人： Arquimedes Martinez Canedo , Hideaki Komatsu , Takeo Yoshizawa
发明人： Arquimedes Martinez Canedo , Hideaki Komatsu , Takeo Yoshizawa
IPC分类号： G06F11/26
CPC分类号： G06F11/261
摘要： A computer-implemented method, system, and article of manufacture for parallelizing a code configured by coupling a functional block having an internal state and a functional block without any internal state. The method includes: creating and storing a graphical representation where functional blocks are chosen as nodes and connections between functional blocks are chosen as links; visiting the nodes on the graphical representation sequentially, detecting inputs from functional blocks without any internal state to functional blocks having an internal state and storing these functional blocks as a set of use blocks, and detecting inputs from functional blocks having an internal state to functional blocks without any internal state and storing these functional blocks as a set of definition blocks; and forming strands of functional blocks based on information on the set of use blocks and information on the set of definition blocks stored in association with the functional blocks.
摘要翻译：一种用于并行化代码的计算机实现的方法，系统和制品，其通过耦合具有内部状态的功能块和功能块而没有任何内部状态来配置。该方法包括：创建和存储其中功能块被选择为节点的图形表示，并且功能块之间的连接被选择为链接; 在图形表示上顺序地访问节点，检测来自功能块的输入，而没有任何内部状态到具有内部状态的功能块，并将这些功能块存储为一组使用块，并且检测具有内部状态的功能块到功能块的输入没有任何内部状态并将这些功能块存储为一组定义块; 以及基于关于所述使用块集合的信息和与所述功能块相关联地存储的所述定义块集合上的信息来形成功能块组。

38. 发明申请

US20110083125A1 PARALLELIZATION PROCESSING METHOD, SYSTEM AND PROGRAM 审中-公开
标题翻译：并行处理方法，系统与程序
公开(公告)号：US20110083125A1
公开(公告)日：2011-04-07
申请号：US12898851
申请日：2010-10-06
申请人： Hideaki Komatsu , Takeo Yoshizawa
发明人： Hideaki Komatsu , Takeo Yoshizawa
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A unified parallelization table is formed by describing a process, to be executed, with a plurality of control blocks and edges connecting the control blocks; selecting highly predictable edges from the edges; identifying strongly-connected clusters; creating a parallelization table, having the entries of the number of processors, the costs thereof and corresponding clusters, for each node in the strongly-connected clusters and a non-strongly connected cluster between the strongly-connected clusters; creating a graph consisting of parallelization tables; converting the graph consisting of the parallelization tables into a series-parallel graph; and merging the parallelization tables for each serial path merging the parallelization tables for each parallel section. Then, based on the number of processors and the cost value in the unified parallelization table, a best entry is selected and an executable code to be allocated to each processor is generated.
摘要翻译：通过用连接控制块的多个控制块和边缘描述要执行的处理来形成统一的并行表; 从边缘选择高度可预测的边缘; 识别强连接的群集; 创建一个并行化表，具有针对强连接集群中的每个节点的处理器数量，成本和对应集群的条目以及强连接集群之间的非强连接集群; 创建一个由并行表组成的图; 将由并行化表组成的图转换成串并行图; 并且合并每个并行段的并行表的每个串行路径的并行化表。然后，基于处理器的数量和统一并行化表中的成本值，选择最佳条目，并生成要分配给每个处理器的可执行代码。

39. 发明授权

US07890940B2 Compilation and runtime information generation and optimization 有权
标题翻译：编译和运行时信息的生成和优化
公开(公告)号：US07890940B2
公开(公告)日：2011-02-15
申请号：US11972912
申请日：2008-01-11
申请人： Hideaki Komatsu , Toshio Suganuma , Toshiaki Yasue
发明人： Hideaki Komatsu , Toshio Suganuma , Toshiaki Yasue
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： To collect frequencies with which processes of a program are executed at high speed. A compiler apparatus for optimizing a program based on frequencies with which each process is executed has a loop process detection portion for detecting a repeatedly executed loop process of the program, a loop process frequency collection portion for collecting loop process frequencies with which the loop process is executed in the program, an in-loop process frequency collection portion for collecting in-loop process frequencies with which, as against times of execution of loop process, each of a plurality of in-loop processes included in the loop process is executed, an in-loop execution information generating portion for generating in-loop execution information indicating the frequencies with which each of the plurality of in-loop processes is executed in the case where the program is executed, and an optimization portion for optimizing the program based on the in-loop execution information.
摘要翻译：收集高速执行程序进程的频率。一种用于基于执行每个处理的频率对程序进行优化的编译装置，具有循环处理检测部分，用于检测程序的重复执行的循环处理;循环处理频率收集部分，用于收集循环处理频率在程序中执行的循环过程频率收集部分，用于收集循环处理频率，与执行循环处理的次数相比，执行循环处理中包括的多个循环中的每个处理，执行循环执行信息生成部分，用于在执行程序的情况下，生成指示执行多个循环中每个处理的频率的循环执行信息;以及优化部分，用于基于循环执行信息。

40. 发明授权

US07864081B2 Fast implementation of decoding function for variable length encoding 有权
标题翻译：快速实现可变长度编码的解码功能
公开(公告)号：US07864081B2
公开(公告)日：2011-01-04
申请号：US12135257
申请日：2008-06-09
申请人： Hiroshi Inoue , Hideaki Komatsu , Moriyoshi Ohara
发明人： Hiroshi Inoue , Hideaki Komatsu , Moriyoshi Ohara
IPC分类号： H03M7/00
CPC分类号： H03M7/40
摘要： An embodiment of the present inventions is a method for encoding/decoding data of variable length format and is used to omit unnecessary pieces of data for the purpose of improving processing performance, reducing the size of data on communication paths and efficiently using limited physical memory. As examples of such variable length encoding, BER compression and UTF-8 encoding of UNICODE text, etc., are cited. While the amount of data can be reduced through encoding, before the data is actually used, it is necessary to restore (decode) it to the original data, which requires a great deal of processing time. One aspect of the present invention is improving decoding by reducing the processing time required to decode the encoded data.
摘要翻译：本发明的实施例是用于对可变长度格式的数据进行编码/解码的方法，并且用于省略不必要的数据片段以便改善处理性能，减少通信路径上的数据的大小并有效地使用有限的物理存储器。作为这种可变长度编码的例子，引用了BER压缩和UNICODE文本的UTF-8编码等。虽然可以通过编码减少数据量，但在实际使用数据之前，需要将其还原（解码）为原始数据，这需要大量的处理时间。本发明的一个方面是通过减少解码编码数据所需的处理时间来改进解码。

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