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    • 33. 发明授权
    • Method and system for switching antenna and channel assignments in broadband wireless networks
    • 宽带无线网络切换天线和信道分配的方法和系统
    • US07573851B2
    • 2009-08-11
    • US11007064
    • 2004-12-07
    • Guanbin XingManyuan ShenHui Liu
    • Guanbin XingManyuan ShenHui Liu
    • H04Q7/00
    • H04L5/06H04B7/0452H04B7/0613H04B17/24H04B17/382H04L5/023H04L27/261H04W28/18H04W48/16H04W72/04H04W72/0453H04W72/085
    • A method and apparatus for antenna switching, grouping, and channel assignments in wireless communication systems. The invention allows multiuser diversity to be exploited with simple antenna operations, therefore increasing the capacity and performance of wireless communications systems. Channel characteristics indicative of signal reception quality for downlink or bi-directional traffic for each channel/antenna resource combination are measured or estimated at a subscriber. Corresponding channel characteristic information is returned to the base station. Channel characteristics information may also be measured or estimated for uplink or bi-directional signals received at each of multiple receive antenna resources. The base station employs channel allocation logic to assign uplink, downlink and/or bi-directional channels for multiple subscribers based on channel characteristics measured and/or estimated for the uplink, downlink and/or bi-directional channels.
    • 一种用于无线通信系统中的天线切换,分组和信道分配的方法和装置。 本发明允许利用简单的天线操作来利用多用户分集,从而增加无线通信系统的容量和性能。 指示用于每个信道/天线资源组合的下行链路或双向业务的信号接收质量的信道特性在用户处被测量或估计。 相应的信道特征信息返回给基站。 还可以对在多个接收天线资源中的每一个处接收的上行链路或双向信号测量或估计信道特性信息。 基站采用信道分配逻辑以基于针对上行链路,下行链路和/或双向信道测量和/或估计的信道特性为多个用户分配上行链路,下行链路和/或双向信道。
    • 40. 发明授权
    • Method and system for improving memory interface data integrity in PLDs
    • 改善PLD内存接口数据完整性的方法和系统
    • US07102544B1
    • 2006-09-05
    • US11142732
    • 2005-05-31
    • Hui Liu
    • Hui Liu
    • H03M7/34
    • G06F11/1032
    • An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.
    • 提供了一种用于优化到外部存储器接口总线的数据呈现的集成电路(IC)。 IC通过外部存储器接口总线与外部存储器通信。 该IC包括编码器,其可以对正在发送到外部存储器的数据进行编码。 编码器根据数据中大多数位的逻辑值对数据进行编码。 编码器能够设置状态位以指示数据被编码。 进一步与编码器串联的是奇偶校验发生器,其基于数据中的逻辑1的数量以及状态位是偶数还是奇数来设置奇偶校验位逻辑值。 IC还包括一个奇偶校验器,用于检测在传输过程中数据是否发生错误。 IC内的解码器将数据解码为原始数据。