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31. 发明申请

US20120215818A1 REQUEST PROCESSING SYSTEM, METHOD AND PROGRAM PRODUCT 审中-公开
标题翻译：请求处理系统，方法和程序产品
公开(公告)号：US20120215818A1
公开(公告)日：2012-08-23
申请号：US13406667
申请日：2012-02-28
申请人： Takeshi Ogasawara
发明人： Takeshi Ogasawara
IPC分类号： G06F17/30
CPC分类号： G06F9/4881 , G06F12/0269 , G06F17/30138 , G06F2209/485 , G06F2209/548
摘要： A processing method has been claimed for reducing the average wait time of requests in a queue in a system environment where garbage collection may occur. In the method, a computer system treats as a unit each request in a queue and a completion time of garbage collection that may occur at the time of processing the request, and processes requests preferentially and systematically in ascending order of the processing times of the units including the garbage collection times, thereby, reducing the average wait time of the requests. While, the computer system managing the queue knows the remaining amount of heap just before processing a certain request, the computer system statistically calculates in advance the amounts of heap to be consumed on a request type basis and holds the values.
摘要翻译：已经要求一种处理方法来减少在可能发生垃圾回收的系统环境中的队列中的请求的平均等待时间。在该方法中，计算机系统将处理请求时可能发生的队列中的每个请求和垃圾收集的完成时间视为单位，并且按照单元的处理时间的升序优先和系统地处理请求包括垃圾收集时间，从而减少请求的平均等待时间。管理队列的计算机系统在处理特定请求之前知道剩余的堆量，计算机系统根据请求类型来预先统计计算要消耗的堆的数量并保存该值。

32. 发明授权

US08140600B2 Memory power control method and memory power control program 失效
标题翻译：存储器功率控制方法和存储器功率控制程序
公开(公告)号：US08140600B2
公开(公告)日：2012-03-20
申请号：US12622470
申请日：2009-11-20
申请人： Takeshi Ogasawara
发明人： Takeshi Ogasawara
IPC分类号： G06F17/30
CPC分类号： G06F12/0276 , G06F2212/1028 , Y02D10/13
摘要： A method and a computer readable article of manufacture for controlling memory power consumption on a computer. The method includes a memory having a power saving mode and performs a garbage collection for collecting no-longer-needed objects in groups the no-longer-needed objects being allocated to memory blocks obtained by dividing a memory's address space by a predetermined constant size. The method includes the steps of dividing a heap area of the memory into a number of sub-heap areas; managing the sub-heap areas; and changing the number of sub-heap areas used for garbage collection based on a magnitude correlation between a required time for the garbage collection and a predefined target value.
摘要翻译：一种用于控制计算机上的存储器功耗的方法和计算机可读制品。该方法包括具有省电模式的存储器，并且执行垃圾收集，用于将不再需要的对象分组用于将不需要的对象分配给通过将存储器的地址空间划分预定的常数大小而获得的存储器块。该方法包括以下步骤：将存储器的堆区划分成多个子堆区; 管理子堆区; 并且基于垃圾收集的所需时间与预定义的目标值之间的大小相关性来改变用于垃圾收集的子堆区域的数量。

33. 发明申请

US20110117434A1 POSITIVE ELECTRODE ACTIVE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, FABRICATION METHOD THEREOF, POSITIVE ELECTRODE FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY 有权
标题翻译：用于非水电解质二次电池的正极电极活性材料，其制造方法，非水电解质二次电池的正电极和非水电解质二次电池
公开(公告)号：US20110117434A1
公开(公告)日：2011-05-19
申请号：US13002254
申请日：2009-07-07
申请人： Takeshi Ogasawara , Naoki Imachi
发明人： Takeshi Ogasawara , Naoki Imachi
IPC分类号： H01M4/52 , B05D5/12
CPC分类号： H01M4/366 , H01M4/13 , H01M4/131 , H01M4/139 , H01M4/1391 , H01M4/36 , H01M4/485 , H01M4/505 , H01M4/525 , H01M10/0525
摘要： A positive electrode active material for non-aqueous electrolyte secondary battery is improved so that a reaction between the positive electrode active material and a non-aqueous electrolyte is restricted in a case where charging voltage is increased.In a non-aqueous electrolyte secondary battery including a positive electrode 1, a negative electrode 2 and a non-aqueous electrolyte, a positive electrode active material wherein a particle of at least one compound selected from Er hydroxide, Er oxyhydroxide, Yb hydroxide, Yb oxyhydroxide, Tb hydroxide, Tb oxyhydroxide, Dy hydroxide, Dy oxyhydroxide, Ho hydroxide, Ho oxyhydroxide, Tm hydroxide, Tm oxyhydroxide, Lu hydroxide, and Lu oxyhydroxide is dispersed and adhered on a surface of a positive electrode active material particle containing Li is used.
摘要翻译：改善非水电解质二次电池用正极活性物质，使得在充电电压增加的情况下，正极活性物质与非水电解质之间的反应受到限制。在包含正极1，负极2和非水电解质的非水电解质二次电池中，使用选自Er氢氧化物，氢氧化锇，氢氧化镱，Yb中的至少一种化合物的微粒的正极活性物质羟基氢氧化物，氢氧化Tb，氢氧化钬，氢氧化钬，氢氧化锇，氢氧化钇，氢氧化钨，氢氧化锆，氢氧化锇分散并附着在含有Li的正极活性物质粒子的表面。

34. 发明申请

US20100106932A1 CONTROL APPARATUS 有权
标题翻译：控制装置
公开(公告)号：US20100106932A1
公开(公告)日：2010-04-29
申请号：US12606242
申请日：2009-10-27
申请人： Takeshi Ogasawara
发明人： Takeshi Ogasawara
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F9/526
摘要： A control apparatus, control method and computer readable article of manufacture for controlling data. The control apparatus includes a data storage unit; a plurality of entry storage units, and a plurality of registration units. The data storage unit stores data. Each of the entry storage units stores an entry for registering a pointer to data. If each of the registration units receives an instruction for registering data, then each registration unit (i) searches the entry storage units for an entry storage unit having an empty entry, (ii) registers a pointer to the data to be registered in the retrieved entry storage unit and (iii) stores the data to be registered and identification information of the retrieved entry storage unit in the data storage unit in such a manner that the data to be registered and the identification information is associated with each other.
摘要翻译：用于控制数据的控制装置，控制方法和计算机可读制造品。控制装置包括数据存储单元; 多个入口存储单元和多个登记单元。数据存储单元存储数据。每个条目存储单元存储用于注册指向数据的条目。如果每个注册单元接收到用于登记数据的指令，则每个注册单元（i）在入口存储单元中搜索具有空条目的条目存储单元，（ii）将注册的数据注册到所检索的数据中入口存储单元，以及（iii）将要登记的数据和所检索的条目存储单元的识别信息以要登记的数据和识别信息相互关联的方式存储在数据存储单元中。

35. 发明授权

US07703095B2 Information processing and control 失效
标题翻译：信息处理和控制
公开(公告)号：US07703095B2
公开(公告)日：2010-04-20
申请号：US12171063
申请日：2008-07-10
申请人： Kiyokuni Kawachiya , Takeshi Ogasawara , Hideaki Komatsu
发明人： Kiyokuni Kawachiya , Takeshi Ogasawara , Hideaki Komatsu
IPC分类号： G06F9/46 , G06F9/45 , G06F11/34
CPC分类号： G06F9/46
摘要： Information processing apparatus, including occurrence number counter counting events that occurred in each of a plurality of CPUs. Apparatus performs functions of; storing accumulated occurrence number of events, which occurred while the thread is being executed by each of the CPUs, in a thread storage area of the thread associating accumulated occurrence number with CPU; storing, in the thread storage area, a value of occurrence number counter of the CPU, the value having been counted before the thread is resumed by the CPU; and adding, to accumulated occurrence number which has been stored in accumulated number storing unit while corresponding to the CPU, a difference value obtained by subtracting a counter value, which has been stored in the start-time number storing unit of the thread, from a counter value of the occurrence number counter of the CPU, in a case where the CPU terminates an execution of the thread.
摘要翻译：信息处理装置，包括在多个CPU中的每一个中发生的发生次数计数事件。仪器执行功能; 在所述线程关联累积发生次数与所述线程的线程存储区域中存储在所述CPU中执行所述线程时发生的事件的累计发生次数; 在线程存储区域中存储CPU的发生次数计数器的值，该值在CPU恢复线程之前已被计数; 并且对与CPU相对应地存储在累积数量存储单元中的累计发生次数相加，将从线程的开始时间数存储单元中存储的计数器值减去得到的差值从在CPU终止执行线程的情况下，CPU的发生次数计数器的计数值。

36. 发明申请

US20090320030A1 METHOD FOR MANAGEMENT OF TIMEOUTS 失效
标题翻译：管理时间的方法
公开(公告)号：US20090320030A1
公开(公告)日：2009-12-24
申请号：US12144780
申请日：2008-06-24
申请人： Takeshi Ogasawara
发明人： Takeshi Ogasawara
IPC分类号： G06F9/46
CPC分类号： G06F9/4825 , G06F9/542 , G06F2209/543
摘要： A method of managing a multithreaded computer system comprises instantiating, in response to each transaction initiated by a first thread of a plurality of threads, a timer object including a scheduled expiration time and a set of timeout handling information for the transaction in storage local to the first thread; registering, in response to each passing of a fixed time interval, each timer object in the storage local to the first thread for which the scheduled expiration time is earlier than the fixed time interval added to a current time in a timer processing component by adding a pointer referencing the timer object to a data structure managed by the timer processing component; and managing each timer object corresponding to a transaction initiated by the first thread that is not registered in the timer processing component in the storage local to the first thread. The timer processing component regularly processes each timer object referenced by the data structure for which the scheduled expiration time value is not earlier than the current time in accordance with the set of timeout handling information of the timer object.
摘要翻译：一种管理多线程计算机系统的方法包括：响应于由多个线程的第一线程发起的每个事务来实例化定时器对象，其包括调度的到期时间和一组超时处理信息，用于存储在本地第一线响应于固定时间间隔的每次通过，将定时处理组件中添加到当前时间的固定时间间隔早于第一线程的本地存储器中的每个定时器对象注册到计时器处理组件中的当前时间的固定时间间隔，将定时器对象引用到由定时器处理组件管理的数据结构; 以及管理与由第一线程发起的事务相对应的每个定时器对象，该事务未被注册到第一线程的本地存储器中的定时器处理组件中。定时器处理组件根据定时器对象的超时处理信息的集合，定期处理由调度的到期时间值不早于当前时间的数据结构引用的每个定时器对象。

37. 发明申请

US20080295108A1 Minimizing variations of waiting times of requests for services handled by a processor 失效
标题翻译：最小化处理器处理的服务请求的等待时间的变化
公开(公告)号：US20080295108A1
公开(公告)日：2008-11-27
申请号：US11753479
申请日：2007-05-24
申请人： Takeshi Ogasawara , Hideaki Komatsu
发明人： Takeshi Ogasawara , Hideaki Komatsu
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F11/3419 , G06F2201/88 , G06F2209/5018 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： Variations of waiting times of requests for services handled by a processor are minimized. In response to the processor receiving a request for a service, an arrival time of the request for the service is recorded and added to a total arrival time for all requests for the service, and a counter of a number of waiting requests for the service is incremented. In response to the processor processing the request, the arrival time of the request is subtracted from the total arrival time, and the counter is decremented. In either case, an average waiting time of requests for the service is determined, a history of the average waiting times is maintained, and the variation within this history is determined. Where the variation is greater than a threshold, processor resources are adjusted to minimize variations within waiting times of requests for all the services handled by the processor.
摘要翻译：由处理器处理的服务请求的等待时间的变化被最小化。响应于处理器接收到对服务的请求，对服务请求的到达时间被记录并添加到对于服务的所有请求的总到达时间，并且对服务的等待请求的数量的计数器是递增响应于处理器处理请求，从总到达时间减去请求的到达时间，并且计数器递减。在任一情况下，确定服务请求的平均等待时间，维持平均等待时间的历史，并且确定该历史中的变化。在变化大于阈值的情况下，调整处理器资源以使处理器处理的所有服务的请求的等待时间内的变化最小化。

38. 发明授权

US07143402B2 Method and apparatus for precision optimization in compiled programs 失效
标题翻译：编译程序精度优化的方法和装置
公开(公告)号：US07143402B2
公开(公告)日：2006-11-28
申请号：US10621281
申请日：2003-07-16
申请人： Takeshi Ogasawara , Toshio Suganuma
发明人： Takeshi Ogasawara , Toshio Suganuma
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A compiler mounted on a computer generates a first object code of a target method in a double precision mode in the floating-point computation. If the target method is found to be frequently called in a single precision mode and a runtime cost may be reduced by executing the target method in the single precision mode, a second object code of the target method is generated in the single precision mode. Alternatively, regardless of whether a target method to be compiled will be called by the double precision mode or the single precision mode in the floating-point computation, the object code is generated by setting the precision mode depending on the type of the computation within the target method. Then, a code for matching the precision mode is generated and added based on a relation between the target code and its caller method.
摘要翻译：安装在计算机上的编译器在浮点计算中以双精度模式生成目标方法的第一目标代码。如果发现目标方法在单精度模式中被频繁地调用，并且可以通过以单精度模式执行目标方法来减少运行时间成本，则以单精度模式生成目标方法的第二目标代码。或者，无论在浮点计算中是否通过双精度模式或单精度模式调用要编译的目标方法，通过根据内部计算的计算类型设置精度模式来生成目标代码目标法。然后，基于目标代码与其调用方法之间的关系生成并添加用于匹配精度模式的代码。

39. 发明申请

US20060070476A1 Vehicular automatic transmission 审中-公开
标题翻译：车载自动变速器
公开(公告)号：US20060070476A1
公开(公告)日：2006-04-06
申请号：US11233358
申请日：2005-09-23
申请人： Takeshi Sato , Takeshi Ogasawara , Daisuke Kondo
发明人： Takeshi Sato , Takeshi Ogasawara , Daisuke Kondo
IPC分类号： B60K17/04
CPC分类号： F16H61/32 , F16H59/105 , F16H2061/1232 , F16H2061/323 , F16H2061/326 , Y10T74/2003
摘要： A vehicular automatic transmission includes an operation part (9) comprising an operation lever (10) projecting into a vehicle interior for changing ranges. The transmission includes an assist having an operation force to be transmitted from the operation lever (10) for producing an assist force to be combined with the operation force, thus outputting a driving force to an automatic transmission (16; 27; 28) for changing the ranges. The transmission includes a mechanical coupler (14; 15) coupling the operation part and the assist to each other. The operation part and the assist are located in an internal space of an instrument panel (1; 34) in the vicinity of a driver seat (2).
摘要翻译：车辆自动变速器包括操作部（9），该操作部（9）包括突出到车辆内部用于变化范围的操作杆（10）。变速器包括具有从操作杆（10）传递的用于产生与操作力组合的辅助力的操作力的辅助，从而向自动变速器（16; 27; 28）输出驱动力，以改变范围。变速器包括将操作部件和辅助件相互联接的机械联接器（14; 15）。操作部分和辅助部位于驾驶员座椅（2）附近的仪表板（1; 34）的内部空间中。

40. 发明授权

US06938131B2 Method, apparatus, program and recording medium for memory access serialization and lock management 失效
标题翻译：用于存储器访问序列化和锁定管理的方法，设备，程序和记录介质
公开(公告)号：US06938131B2
公开(公告)日：2005-08-30
申请号：US10413850
申请日：2003-04-15
申请人： Takeshi Ogasawara
发明人： Takeshi Ogasawara
IPC分类号： G06F9/38 , G06F9/46 , G06F9/52 , G06F12/00 , G06F12/06 , G06F12/14 , G06F15/177
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F9/3851 , G06F9/526
摘要： To improve the processing speed in a case where a program requiring memory access serialization is executed in a multiprocessor environment with a load instruction out-of-order execution function.Each of CPUs has the function of performing store forwarding (SF) when the address regions of a pair of store and load instructions coincide with each other. Each CPU stops SF and performs store forwarding avoidance (SFA) when the two address regions do not coincide with each other but have an overlap therebetween. Each of SF and SFA is executed with priority over out-of-order execution. Each CPU performs SFA effective in limiting out-of-order execution with respect to a predetermined store instruction on a program and a load instruction mated to the store instruction and given after the store instruction, and ensures that data relating to the store instruction can be observed from other CPUs.
摘要翻译：在需要存储器访问序列化的程序在具有加载指令无序执行功能的多处理器环境中执行的情况下，提高处理速度。当一对存储和加载指令的地址区域彼此重合时，每个CPU具有执行存储转发（SF）的功能。当两个地址区域彼此不一致但在它们之间有重叠时，每个CPU停止SF并执行存储转发避免（SFA）。 SF和SFA中的每一个优先于无序执行。每个CPU执行SFA有效地限制关于程序上的预定存储指令和与存储指令配合并在存储指令之后给出的加载指令的无序执行，并且确保与存储指令相关的数据可以是从其他CPU观察。

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