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31. 发明授权

US07907434B2 Semiconductor apparatus having a large-size bus connection 有权
标题翻译：具有大尺寸总线连接的半导体装置
公开(公告)号：US07907434B2
公开(公告)日：2011-03-15
申请号：US11984932
申请日：2007-11-26
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
摘要翻译：在本发明的半导体装置中，设置有多个电路部件。第一条总线将电路组件互连。第二总线将电路组件互连。当从一个电路部件发送信号到另一个电路部件时，切换单元输出使每个电路部件选择第一总线和第二总线中的一个的选择信号。第二个总线的大小大于第一个总线的大小。

32. 发明授权

US07782682B2 Semiconductor device with circuitry for efficient information exchange 有权
标题翻译：具有用于有效信息交换的电路的半导体器件
公开(公告)号：US07782682B2
公开(公告)日：2010-08-24
申请号：US10006238
申请日：2001-12-10
申请人： Yasurou Matsuzaki , Masao Taguchi
发明人： Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C7/77
CPC分类号： H03M5/14 , G11C8/10 , H03M7/00 , H03M7/30
摘要： A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.
摘要翻译：具有寄存器和信息产生电路的半导体器件可以减少要传输的数据，从而节省电力。寄存器存储第一个信息。信息生成电路响应于从设备的外部获取的信号，生成指示第一信息的哪些位将被反转的第二信息。

33. 发明申请

US20080142847A1 Semiconductor apparatus having a large-size bus connection 有权
标题翻译：具有大尺寸总线连接的半导体装置
公开(公告)号：US20080142847A1
公开(公告)日：2008-06-19
申请号：US11984932
申请日：2007-11-26
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： H01L23/50
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
摘要翻译：在本发明的半导体装置中，设置有多个电路部件。第一条总线将电路组件互连。第二总线将电路组件互连。当从一个电路部件发送信号到另一个电路部件时，切换单元输出使每个电路部件选择第一总线和第二总线中的一个的选择信号。第二个总线的大小大于第一个总线的大小。

34. 发明授权

US07317650B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07317650B2
公开(公告)日：2008-01-08
申请号：US11715851
申请日：2007-03-09
申请人： Naoharu Shinozaki , Yasurou Matsuzaki
发明人： Naoharu Shinozaki , Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/40607 , G11C7/08 , G11C8/18 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
摘要翻译：在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

35. 发明授权

US07209402B2 Semiconductor memory 有权
公开(公告)号：US07209402B2
公开(公告)日：2007-04-24
申请号：US10968811
申请日：2004-10-20
申请人： Naoharu Shinozaki , Yasurou Matsuzaki
发明人： Naoharu Shinozaki , Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/40607 , G11C7/08 , G11C8/18 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

36. 发明申请

US20060294322A1 Multi-port memory based on DRAM core 有权
公开(公告)号：US20060294322A1
公开(公告)日：2006-12-28
申请号：US11512319
申请日：2006-08-30
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G06F13/28
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

37. 发明授权

US07138723B2 Deformable semiconductor device 有权
标题翻译：可变形半导体器件
公开(公告)号：US07138723B2
公开(公告)日：2006-11-21
申请号：US11006664
申请日：2004-12-08
申请人： Kazuyuki Aiba , Akira Takashima , Kaname Ozawa , Tetsuya Hiraoka , Takaaki Suzuki , Yasurou Matsuzaki
发明人： Kazuyuki Aiba , Akira Takashima , Kaname Ozawa , Tetsuya Hiraoka , Takaaki Suzuki , Yasurou Matsuzaki
IPC分类号： H01L23/31 , H01L25/065 , H01L29/06 , H01L23/28 , H01L29/02
CPC分类号： H01L29/0657 , H01L23/3128 , H01L23/4334 , H01L24/81 , H01L25/065 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/13144 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06582 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/1532 , H01L2924/3511
摘要： A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.
摘要翻译：通过在其表面上形成的涂层材料将半导体芯片固定成大致圆柱形状的状态。变形的半导体芯片倒装芯片连接到插入器并用密封树脂密封到插入器上。焊球作为外部端子设置在插入器的另一侧。

38. 发明申请

US20050242864A1 Semiconductor device, semiconductor system, and digital delay circuit 审中-公开
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US20050242864A1
公开(公告)日：2005-11-03
申请号：US11055784
申请日：2005-02-11
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G06F13/42 , G11C7/10 , G11C7/22 , H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

39. 发明申请

US20050190625A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20050190625A1
公开(公告)日：2005-09-01
申请号：US11098557
申请日：2005-04-05
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C7/10 , G11C11/406 , G11C11/4063 , G11C7/00
CPC分类号： G11C7/1045 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4067
摘要： Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.
摘要翻译：标志分别形成为分别对应于包括易失性存储单元的存储单元组。每个标志指示存储器单元将数据存储在第二存储器模式中的设置状态。在从每个存储器单元独立地保持数据的第一存储器模式改变为在每个存储单元组的存储单元中保留相同数据的第二存储器模式的改变操作中，每个标志响应于首先访问相应的存储单元组。因此，在每个存储单元组中仅在第二存储器模式中进行第一次访问。存储单元按照改变操作中的标志在模式下访问，从而即使在改变操作期间也允许管理半导体存储器的系统自由地访问存储单元。因此，可以消除实际的改变时间。

40. 发明授权

US06907555B1 Self-test circuit and memory device incorporating it 有权
标题翻译：自检电路和结合其的存储器件
公开(公告)号：US06907555B1
公开(公告)日：2005-06-14
申请号：US09691115
申请日：2000-10-19
申请人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
发明人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
IPC分类号： G01R31/28 , G01R31/3185 , G06F12/16 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/44
CPC分类号： G11C29/44
摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.
摘要翻译：本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息关于这个比较的结果。然后将该比较结果信息输出到外部。

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