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31. 发明授权

US08729521B2 Self aligned fin-type programmable memory cell 有权
标题翻译：自对准鳍式可编程存储单元
公开(公告)号：US08729521B2
公开(公告)日：2014-05-20
申请号：US12778897
申请日：2010-05-12
申请人： Hsiang-Lan Lung , Matthew J. Breitwisch , Chung-Hon Lam
发明人： Hsiang-Lan Lung , Matthew J. Breitwisch , Chung-Hon Lam
IPC分类号： H01L45/00 , H01L21/20
CPC分类号： H01L45/1666 , H01L27/2409 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/124 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1691
摘要： A fin-type programmable memory cell includes a bottom electrode electrically coupled to an access device, a top electrode, and an L-shaped memory material element electrically coupled to the bottom and top electrodes. A memory array includes an array of such memory cells, electrically coupled to an array of access devices. Method for making a memory cell, includes: forming a dielectric support layer over a bottom electrode, the dielectric support layer having an upper surface; forming a cavity through the dielectric support layer, exposing a surface of the bottom electrode and defining a dielectric support structure having a sidewall; forming a film of memory material over the dielectric support structure and in the cavity; depositing a dielectric spacer layer over the memory material film; forming a dielectric sidewall spacer from the dielectric spacer layer and a memory material structure having a generally horizontal portion underlying the dielectric sidewall spacer and a generally vertical portion between the dielectric sidewall spacer and the sidewall of the dielectric support structure; forming a dielectric fill; planarizing the dielectric fill to expose upper ends of the vertical portion of the memory material structure; depositing a top electrode material over the planarized dielectric fill; and forming a top electrode from the top electrode material and a memory material element from the memory material structure.
摘要翻译：翅片式可编程存储单元包括电耦合到存取装置的底部电极，顶部电极和电耦合到底部和顶部电极的L形记忆材料元件。存储器阵列包括电耦合到接入设备阵列的这种存储器单元的阵列。制造存储单元的方法包括：在底部电极上形成电介质支撑层，所述电介质支撑层具有上表面; 通过所述电介质支撑层形成空腔，暴露所述底部电极的表面并限定具有侧壁的电介质支撑结构; 在电介质支撑结构和空腔中形成记忆材料膜; 在记忆材料膜上沉积介电间隔层; 从所述电介质隔离层形成电介质侧壁间隔物，以及存储材料结构，其具有在所述电介质侧壁间隔物下方的大致水平部分，以及所述电介质侧壁间隔物和所述电介质支撑结构的侧壁之间的大致垂直部分; 形成电介质填料; 平面化电介质填充物以暴露存储材料结构的垂直部分的上端; 在平坦化的电介质填充物上沉积顶部电极材料; 以及从所述顶部电极材料形成顶部电极和从所述存储器材料结构形成的记忆材料元件。

32. 发明申请

US20100328995A1 METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY 有权
标题翻译：减少相变记忆中缺陷位的方法和装置
公开(公告)号：US20100328995A1
公开(公告)日：2010-12-30
申请号：US12715802
申请日：2010-03-02
申请人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

33. 发明申请

US20090072216A1 PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING 有权
标题翻译：相变式存储单元阵列与自适应底层电极及其制造方法
公开(公告)号：US20090072216A1
公开(公告)日：2009-03-19
申请号：US11855983
申请日：2007-09-14
申请人： Hsiang Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
发明人： Hsiang Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。最后，在存储器元件上形成位线以完成存储器单元。在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

34. 发明申请

US20120193595A1 COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS 有权
标题翻译：用于形成相变材料的复合靶材溅射
公开(公告)号：US20120193595A1
公开(公告)日：2012-08-02
申请号：US13076169
申请日：2011-03-30
申请人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
发明人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
IPC分类号： H01L45/00 , C23C14/14 , C23C14/34
CPC分类号： H01L47/00 , C23C14/06 , C23C14/0623 , C23C14/3414 , H01L21/06 , H01L27/24 , H01L45/144 , H01L45/1625
摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.
摘要翻译：使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

35. 发明授权

US08426242B2 Composite target sputtering for forming doped phase change materials 有权
标题翻译：用于形成掺杂相变材料的复合靶溅射
公开(公告)号：US08426242B2
公开(公告)日：2013-04-23
申请号：US13076169
申请日：2011-03-30
申请人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
发明人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
IPC分类号： H01L21/06
CPC分类号： H01L47/00 , C23C14/06 , C23C14/0623 , C23C14/3414 , H01L21/06 , H01L27/24 , H01L45/144 , H01L45/1625
摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.
摘要翻译：使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

36. 发明授权

US08363463B2 Phase change memory having one or more non-constant doping profiles 有权
标题翻译：具有一个或多个非恒定掺杂分布的相变存储器
公开(公告)号：US08363463B2
公开(公告)日：2013-01-29
申请号：US12729837
申请日：2010-03-23
申请人： Yen-Hao Shih , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung H Lam
发明人： Yen-Hao Shih , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung H Lam
IPC分类号： G11C11/00
CPC分类号： H01L45/1625 , G11C13/0004 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1641
摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
摘要翻译：一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布。根据不同的晶体学，热学和电学条件以及不同的相变条件，使用非恒定浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

37. 发明授权

US08633464B2 In via formed phase change memory cell with recessed pillar heater 失效
标题翻译：在通孔形成相位改变存储单元与凹柱加热器
公开(公告)号：US08633464B2
公开(公告)日：2014-01-21
申请号：US13350967
申请日：2012-01-16
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译：一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极。

38. 发明授权

US08344351B2 Phase change memory device with plated phase change material 有权
标题翻译：相变存储器件，具有电镀相变材料
公开(公告)号：US08344351B2
公开(公告)日：2013-01-01
申请号：US13159594
申请日：2011-06-14
申请人： Matthew J. Breitwisch , Eric A. Joseph , Alejandro G. Schrott , Xiaoyan Shao
发明人： Matthew J. Breitwisch , Eric A. Joseph , Alejandro G. Schrott , Xiaoyan Shao
IPC分类号： H01L29/04 , H01L47/00 , H01L29/06
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1683 , H01L45/1691
摘要： A phase change memory device includes a plurality of memory cells comprising a substrate having a contact surface with an array of conductive contacts to be connected with access circuitry and a nitride layer formed at the contact surface. A plurality of vias are formed through the nitride layer to the contact surface and correspond to each conductive contact, the vias including a conformal conductive seed layer lining each via along exposed portions of the nitride layer and the contact surface and having oxidized edges. A dielectric layer is recessed within the conformal conductive seed layer and exposes a center region of each via. A phase change material is recessed within the center region of each via. A conductive material that remains conductive upon oxidation is formed over the phase change material. A top electrode is formed on each memory cell.
摘要翻译：相变存储器件包括多个存储单元，其包括具有与要与接触电路连接的导电触点阵列的接触表面的衬底和在接触表面形成的氮化物层。多个通孔通过氮化物层形成到接触表面并且对应于每个导电接触，通孔包括沿着氮化物层和接触表面的暴露部分并且具有氧化边缘的每个通孔衬里的共形导电种子层。电介质层凹入保形导电晶种层内并露出每个通孔的中心区域。相变材料凹陷在每个通孔的中心区域内。在相变材料上形成氧化时保持导电的导电材料。在每个存储单元上形成顶部电极。

39. 发明授权

US07960203B2 Pore phase change material cell fabricated from recessed pillar 有权
标题翻译：由凹柱制造的孔相变材料池
公开(公告)号：US07960203B2
公开(公告)日：2011-06-14
申请号：US12021577
申请日：2008-01-29
申请人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
发明人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
IPC分类号： H01L21/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
摘要翻译：提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。

40. 发明申请

US20110057162A1 IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER 有权
标题翻译：通过形成相位改变记忆细胞与被加热的支柱加热器
公开(公告)号：US20110057162A1
公开(公告)日：2011-03-10
申请号：US12556198
申请日：2009-09-09
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译：一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极。

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