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31. 发明申请

US20080122098A1 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20080122098A1
公开(公告)日：2008-05-29
申请号：US12000396
申请日：2007-12-12
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

32. 发明授权

US07245534B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07245534B2
公开(公告)日：2007-07-17
申请号：US11135415
申请日：2005-05-24
申请人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
发明人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

33. 发明申请

US20060268608A1 Data storage system 失效
公开(公告)号：US20060268608A1
公开(公告)日：2006-11-30
申请号：US11497325
申请日：2006-08-02
申请人： Mitsuhiro Noguchi , Akira Goda
发明人： Mitsuhiro Noguchi , Akira Goda
IPC分类号： G11C16/06
CPC分类号： G06F11/1008 , G11C16/0483
摘要： A data storage system, which includes a plurality of pages, each of which includes a plurality of first memory cells, from which at least binary data can be read-out a plurality of times without destruction; a circuit which receives data-output of at least one first page, detects an error in at least one bit of data, and outputs information of the error position; another circuit which determines whether data of an error bit is “1” or “0”. When the determination is “1” or “0”, the first memory cell of the first page is erased, and error-corrected data is written.

34. 发明授权

US07057936B2 Nonvolatile semiconductor memory device 失效
公开(公告)号：US07057936B2
公开(公告)日：2006-06-06
申请号：US10896081
申请日：2004-07-22
申请人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
发明人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/3468
摘要： A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.

35. 发明授权

US06969660B2 Method of manufacturing a semiconductor device with trench isolation between two regions having different gate insulating films 失效
标题翻译：在具有不同栅极绝缘膜的两个区域之间制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US06969660B2
公开(公告)日：2005-11-29
申请号：US11007462
申请日：2004-12-09
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
IPC分类号： H01L27/115 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11573
摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.
摘要翻译：半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。第一栅极绝缘膜和第一栅电极形成在第一区域中。在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。在边界区域形成器件隔离区。该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。沟槽的底部具有与部分不同的深度。

36. 发明授权

US06943453B2 Superconductor device and method of manufacturing the same 失效
公开(公告)号：US06943453B2
公开(公告)日：2005-09-13
申请号：US10318257
申请日：2002-12-13
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L29/40
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.

37. 发明申请

US20050141291A1 Semiconductor memory 有权
公开(公告)号：US20050141291A1
公开(公告)日：2005-06-30
申请号：US11068228
申请日：2005-03-01
申请人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
发明人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/26 , G11C16/0483 , H01L27/115
摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

38. 发明申请

US20050133874A1 Method of manufactoring a semiconductor device with trench isolation between two regions having different gate insulating films 失效
标题翻译：在具有不同栅极绝缘膜的两个区域之间制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US20050133874A1
公开(公告)日：2005-06-23
申请号：US11007462
申请日：2004-12-09
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
IPC分类号： H01L27/115 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11573
摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.
摘要翻译：半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。第一栅极绝缘膜和第一栅电极形成在第一区域中。在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。在边界区域形成器件隔离区。该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。沟槽的底部具有与部分不同的深度。

39. 发明授权

US06882592B2 Semiconductor memory device 失效
公开(公告)号：US06882592B2
公开(公告)日：2005-04-19
申请号：US10696028
申请日：2003-10-30
申请人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C16/02 , G06F11/10 , G11C8/00 , G11C11/34 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/42 , G11C29/52 , H01L21/8247 , H01L27/00 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

40. 发明授权

US07919389B2 Semiconductor memory device that is resistant to high voltages and a method of manufacturing the same 有权
标题翻译：耐高电压的半导体存储器件及其制造方法
公开(公告)号：US07919389B2
公开(公告)日：2011-04-05
申请号：US12498149
申请日：2009-07-06
申请人： Akira Goda , Mitsuhiro Noguchi
发明人： Akira Goda , Mitsuhiro Noguchi
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.
摘要翻译：提出了具有存储单元区域和外围电路区域的半导体存储器件以及制造这种半导体存储器件的方法，其中沟槽形成在存储单元区域中较浅以提高产量，并且在周边电路区域的高电压晶体管区域，特别是在其高压晶体管区域中形成深沟槽，以便提高元件隔离耐受电压。在存储单元区域中设置有多个具有作为电荷累积绝缘层的ONO层15的存储单元晶体管，其中用于这些存储单元晶体管的元件隔离槽6窄而浅。在外围电路区域中设置两个类型的晶体管，一个用于高电压，另一个用于低电压，具有与存储单元区域中的ONO层15不同的栅极绝缘层16或17，其中至少元件用于高压晶体管的隔离槽23宽而深。以这种方式，可以提高存储单元区域的集成度和产量，并且确保外围电路区域中的耐受电压。

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