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31. 发明申请

US20120032615A1 Shift Register 有权
标题翻译：移位寄存器
公开(公告)号：US20120032615A1
公开(公告)日：2012-02-09
申请号：US13264828
申请日：2009-12-25
申请人： Tetsuo Kikuchi , Shinya Tanaka , Chikao Yamasaki , Junya Shimada
发明人： Tetsuo Kikuchi , Shinya Tanaka , Chikao Yamasaki , Junya Shimada
IPC分类号： H05B37/02 , G11C19/28
CPC分类号： G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/0291 , G09G2330/021 , G11C19/28
摘要： Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.
摘要翻译：提供一种移位寄存器，其通过级联连接单元电路来构成，每个单元电路包括自举电路。在至少一个示例性实施例中，对于单元电路，晶体管处于导通状态和时钟信号为高电平的时间段对应于时钟传递周期。在其一个导通端子连接到晶体管的栅极的晶体管中，晶体管的沟道长度被配置为使得低电平电位被馈送到晶体管的栅极，以在晶体管的时钟通过期间将晶体管转换为截止状态，并且在晶体管的导通端子中施加低电位电位使晶体管的通过时间长于晶体管的沟道长度。由此，可以减小时钟通过期间的漏电流，并且防止晶体管的栅极电位的波动和输出信号中的钝度发生。

32. 发明申请

US20110007049A1 TFT, SHIFT REGISTER, SCAN SIGNAL LINE DRIVING CIRCUIT, AND DISPLAY DEVICE 审中-公开
标题翻译： TFT，SHIFT寄存器，扫描信号线驱动电路和显示装置
公开(公告)号：US20110007049A1
公开(公告)日：2011-01-13
申请号：US12736158
申请日：2009-01-30
申请人： Tetsuo Kikuchi , Shinya Tanaka , Hajime Imai , Hideki Kitagawa , Chikao Yamasaki , Yoshiharu Kataoka
发明人： Tetsuo Kikuchi , Shinya Tanaka , Hajime Imai , Hideki Kitagawa , Chikao Yamasaki , Yoshiharu Kataoka
IPC分类号： G09G5/00 , H01L33/08 , H01L33/16
CPC分类号： H01L27/124 , G02F1/1368 , G09G3/3677 , G09G2310/0286 , H01L27/1255
摘要： A TFT includes, in at least one embodiment, a capacitor formed: so as to have a region where a first capacitor electrode connected to a source electrode and a second capacitor electrode connected to a gate electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween; and so as to have a region where the first capacitor electrode and a third capacitor electrode connected to the gate electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween with a coupling between the first capacitor electrode and the third capacitor electrode and a coupling between the first capacitor electrode and the second capacitor electrode formed over mutually opposite faces of the first capacitor electrode. This realizes a TFT which can save a footprint of a capacitor connected to a TFT body section.
摘要翻译：在至少一个实施例中，TFT包括形成的电容器，以便具有连接到源电极的第一电容器电极和连接到栅电极的第二电容器电极被布置成在厚度方向上堆叠的区域，在它们之间的第一电介质层彼此相对; 并且具有第一电容器电极和连接到栅电极的第三电容器电极被布置成在厚度方向上堆叠并且在其间的第二介电层相互相对的区域，其中第一电容器电极和第一电容器电极之间的耦合第三电容器电极以及在第一电容器电极的彼此相对的面上形成的第一电容器电极和第二电容器电极之间的耦合。这实现了TFT，其可以节省连接到TFT主体部分的电容器的占位面积。

33. 发明申请

US20140306225A1 THIN FILM TRANSISTOR AND SHIFT REGISTER 有权
标题翻译：薄膜晶体管和移位寄存器
公开(公告)号：US20140306225A1
公开(公告)日：2014-10-16
申请号：US13809930
申请日：2011-05-20
申请人： Tetsuo Kikuchi , Yoshiharu Kataoka , Shinya Tanaka , Junya Shimada , Chikao Yamasaki
发明人： Tetsuo Kikuchi , Yoshiharu Kataoka , Shinya Tanaka , Junya Shimada , Chikao Yamasaki
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/78696 , H01L27/0207 , H01L27/12 , H01L27/1222 , H01L27/1225 , H01L29/7869
摘要： Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.
摘要翻译：提供具有高电流驱动能力和合适阈值电压的薄膜晶体管。薄膜晶体管包括栅电极，形成在栅电极上的绝缘层，形成在绝缘层上的半导体层以及形成在半导体层上的源/漏电极。半导体层包括在源极/漏极的纵向彼此分离的多个区域。

34. 发明授权

US08654108B2 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US08654108B2
公开(公告)日：2014-02-18
申请号：US13393812
申请日：2010-04-13
申请人： Shinya Tanaka , Tetsuo Kikuchi , Junya Shimada , Takuya Watanabe
发明人： Shinya Tanaka , Tetsuo Kikuchi , Junya Shimada , Takuya Watanabe
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0417 , G09G2310/0286
摘要： In a liquid crystal display device provided with a monolithic gate driver, a panel frame area is to be reduced as compared with a conventional configuration so that the device size can be reduced. In a region on an array substrate located outside of a display region, a third metal (503) is formed as a metal film in addition to a source metal (501) and a gate metal (502). The source metal (501) forms a wiring pattern that includes source electrodes of thin film transistors disposed in a pixel circuit and a gate driver, and the gate metal (502) forms a wiring pattern that includes gate electrodes of the thin film transistors. The third metal (503) is electrically connected to at least one of the source metal (501) and the gate metal (502) through a contact.
摘要翻译：在具有单片栅极驱动器的液晶显示装置中，与传统的结构相比，面板框架区域将被减小，从而可以减小装置的尺寸。在位于显示区域外部的阵列基板上的区域中，除了源极金属（501）和栅极金属（502）之外，还形成第三金属（503）作为金属膜。源极金属（501）形成包括设置在像素电路中的薄膜晶体管的源电极和栅极驱动器的布线图案，并且栅极金属（502）形成包括薄膜晶体管的栅电极的布线图案。第三金属（503）通过触点与源极金属（501）和栅极金属（502）中的至少一个电连接。

35. 发明授权

US08586987B2 Active matrix substrate and active matrix display device 有权
标题翻译：有源矩阵基板和有源矩阵显示装置
公开(公告)号：US08586987B2
公开(公告)日：2013-11-19
申请号：US13394621
申请日：2010-05-21
申请人： Tetsuo Kikuchi , Shinya Tanaka , Junya Shimada , Chikao Yamasaki
发明人： Tetsuo Kikuchi , Shinya Tanaka , Junya Shimada , Chikao Yamasaki
IPC分类号： H01L29/04 , H01L29/15 , G02F1/1343 , H01L21/84
CPC分类号： H01L27/3276 , G02F1/133553 , G02F1/13452 , G02F1/13454 , G02F1/13458 , G02F2001/13629 , H01L27/124
摘要： A second stem wires (17c), formed by a reflective pixel electrode layer formed as a different layer from first stem wires (17a), is provided in such a way as to extend along a long side of its adjacent one of the first stem wires (17a). This makes it possible to achieve a TFT array substrate (1) on which a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) have been monolithically formed, wherein the width of a frame part in which the a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) are formed can be reduced.
摘要翻译：由与第一杆线（17a）形成为不同层的反射像素电极层形成的第二杆线（17c）设置成沿其相邻的第一杆线的长边延伸（17a）。这使得可以实现其栅极驱动电路（15）及其导线（17a，17b，17c，18）已经被整体地形成在其上的框架部分的宽度，其中a 栅极驱动电路（15）及其导线（17a，17b，17c，18）可以被形成。

36. 发明申请

US20120218237A1 DISPLAY PANEL AND DISPLAY APPARATUS 有权
标题翻译：显示面板和显示设备
公开(公告)号：US20120218237A1
公开(公告)日：2012-08-30
申请号：US13504133
申请日：2010-06-02
申请人： Junya Shimada , Shinya Tanaka , Tetsuo Kikuchi , Chikao Yamasaki
发明人： Junya Shimada , Shinya Tanaka , Tetsuo Kikuchi , Chikao Yamasaki
IPC分类号： G09G5/00
CPC分类号： G02F1/13452 , G02F1/13454
摘要： The present invention is to provide a display panel and a display apparatus which can reduce the picture-frame area while sufficiently preventing the delay of signals by allowing a required amount of current to flow. The display panel of the present invention is a display panel which includes a circuit substrate, and an opposed substrate facing the circuit substrate, and which is featured in that the circuit section is arranged in the picture-frame area of the display panel, in that the circuit section includes trunk wiring, and branch wiring connected to the gate electrode or the source electrode of a transistor in the circuit section, and in that all or a part of the trunk wiring is provided on the opposed substrate, and the branch wiring is provided on the circuit substrate so as to be electrically connected to the trunk wiring via a conductor.
摘要翻译：本发明提供一种显示面板和显示装置，其能够通过允许所需量的电流流动来充分防止信号的延迟，从而减小画面区域。本发明的显示面板是包括电路基板和面对电路基板的相对基板的显示面板，其特征在于，电路部分布置在显示面板的图像框区域中，其中电路部分包括主干布线和连接到电路部分中的晶体管的栅电极或源电极的分支布线，并且所述干线布线的全部或一部分设置在相对的基板上，分支布线为设置在电路基板上，以经由导体与主干布线电连接。

37. 发明授权

US09111810B2 Circuit board and display device including first and second channel layers made of different semiconductor materials 有权
标题翻译：电路板和显示装置，包括由不同半导体材料制成的第一和第二通道层
公开(公告)号：US09111810B2
公开(公告)日：2015-08-18
申请号：US13643652
申请日：2011-03-02
申请人： Hideki Kitagawa , Shinya Tanaka , Hajime Imai , Atsuhito Murai , Mitsunori Imade , Tetsuo Kikuchi , Kazunori Morimoto , Junya Shimada , Jun Nishimura
发明人： Hideki Kitagawa , Shinya Tanaka , Hajime Imai , Atsuhito Murai , Mitsunori Imade , Tetsuo Kikuchi , Kazunori Morimoto , Junya Shimada , Jun Nishimura
IPC分类号： H01L29/10 , H01L29/12 , H01L27/12 , H01L27/146 , H01L27/144
CPC分类号： H01L27/1251 , H01L27/1225 , H01L27/1259 , H01L27/1446 , H01L27/14632 , H01L27/14678
摘要： A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.
摘要翻译：电路板（1）在绝缘基板（2）上包括多个晶体管元件。多个晶体管元件中的至少一个是氧化物TFT（10），其包括作为沟道层（11）的氧化物半导体。多个晶体管元件中的至少一个是与作为电路元件的功能的氧化物TFT（10）不同的a-SiTFT（20）（i），（ii）包括作为沟道层（21）的无定形硅半导体。氧化物TFT（10）是顶栅晶体管，并且a-SiTFT（20）是底栅晶体管。这提供：一种配置，其可以（a）增强配备有作为电路部件的各自功能不同的TFT的电路板的性能，（b）减小安装TFT所需的面积; 以及电路基板的制造方法。

38. 发明授权

US08786582B2 Display panel and display apparatus 有权
标题翻译：显示面板和显示设备
公开(公告)号：US08786582B2
公开(公告)日：2014-07-22
申请号：US13504133
申请日：2010-06-02
申请人： Junya Shimada , Shinya Tanaka , Tetsuo Kikuchi , Chikao Yamasaki
发明人： Junya Shimada , Shinya Tanaka , Tetsuo Kikuchi , Chikao Yamasaki
IPC分类号： G09G5/00 , G02F1/1345
CPC分类号： G02F1/13452 , G02F1/13454
摘要： The present invention is to provide a display panel and a display apparatus which can reduce the picture-frame area while sufficiently preventing the delay of signals by allowing a required amount of current to flow. The display panel of the present invention is a display panel which includes a circuit substrate, and an opposed substrate facing the circuit substrate, and which is featured in that the circuit section is arranged in the picture-frame area of the display panel, in that the circuit section includes trunk wiring, and branch wiring connected to the gate electrode or the source electrode of a transistor in the circuit section, and in that all or a part of the trunk wiring is provided on the opposed substrate, and the branch wiring is provided on the circuit substrate so as to be electrically connected to the trunk wiring via a conductor.
摘要翻译：本发明提供一种显示面板和显示装置，其能够通过允许所需量的电流流动来充分防止信号的延迟，从而减小画面区域。本发明的显示面板是包括电路基板和面对电路基板的相对基板的显示面板，其特征在于，电路部分布置在显示面板的图像框区域中，其中电路部分包括主干布线和连接到电路部分中的晶体管的栅电极或源电极的分支布线，并且所述干线布线的全部或一部分设置在相对的基板上，分支布线为设置在电路基板上，以经由导体与主干布线电连接。

39. 发明申请

US20130214279A1 CIRCUIT BOARD AND DISPLAY DEVICE 审中-公开
标题翻译：电路板和显示设备
公开(公告)号：US20130214279A1
公开(公告)日：2013-08-22
申请号：US13695082
申请日：2011-02-23
申请人： Jun Nishimura , Hideki Kitagawa , Atsuhito Murai , Hajime Imai , Shinya Tanaka , Mitsunori Imade , Tetsuo Kikuchi , Junya Shimada , Kazunori Morimoto
发明人： Jun Nishimura , Hideki Kitagawa , Atsuhito Murai , Hajime Imai , Shinya Tanaka , Mitsunori Imade , Tetsuo Kikuchi , Junya Shimada , Kazunori Morimoto
IPC分类号： H01L27/02
CPC分类号： H01L29/78663 , G02F1/13338 , G02F1/13624 , G06F3/0412 , H01L27/0207 , H01L27/0705 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L29/78633 , H01L29/7869
摘要： A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
摘要翻译：氧化物TFT元件（3）的源极和漏极电极层（3s / 3d）由第一导电层形成。氧化物TFT元件（3）的栅极（3g）和a-Si TFT元件（5）的栅电极（5g）由单个导电层即第二导电层形成。 a-Si TFT元件（5）的源极和漏极电极层（5s / 5d）由第三导电层形成。第三导电层形成在第二导电层上方的厚度方向上，其中每个导电层堆叠在绝缘基板（2）上。此外，第一导电层在厚度方向上形成在第二导电层的下方。因此，可以提供可以使形成在绝缘基板上的晶体管元件的集成度提高的电路板。

40. 发明申请

US20130028370A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20130028370A1
公开(公告)日：2013-01-31
申请号：US13637367
申请日：2011-01-06
申请人： Tetsuo Kikuchi , Shinya Tanaka , Junya Shimada , Chikao Yamasaki
发明人： Tetsuo Kikuchi , Shinya Tanaka , Junya Shimada , Chikao Yamasaki
IPC分类号： G11C19/28
CPC分类号： G11C19/184 , G09G3/3677 , G09G2310/0267 , G09G2310/0286 , G11C19/28
摘要： A shift register is formed by connecting unit circuits 11 in multi-stage. One electrode of a capacitor Cap2 in the unit circuit 11 is connected to the gate terminal (node N1) of a transistor T2, and the other connected to a node N2. A compensation circuit composed of transistors T3 to T5 provides a clock signal CKB to the node N2 when the node N1 potential is at low level, and applies a low-level potential to the node N2 when the node N1 potential is at high level. Accordingly, even when the gate potential of the transistor T2 changes with a change in a clock signal CK, a signal that cancels out the change is provided through the capacitor Cap2, stabilizing the gate potential of the transistor T2. Thus, a change in the control terminal potential of an output transistor associated with a change in a clock signal is prevented.
摘要翻译：通过多级连接单元电路11形成移位寄存器。单元电路11中的电容器Cap2的一个电极连接到晶体管T2的栅极端子（节点N1），另一个连接到节点N2。当晶体管T3至T5组成的补偿电路在节点N1电位处于低电平时向节点N2提供时钟信号CKB，并且当节点N1电位处于高电平时向节点N2施加低电平电位。因此，即使当晶体管T2的栅极电位随着时钟信号CK的变化而变化时，通过电容器Cap2提供抵消变化的信号，从而稳定晶体管T2的栅极电位。因此，防止与时钟信号的变化相关联的输出晶体管的控制端电位的变化。

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