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31. 发明授权

US06941434B2 Self-synchronous FIFO memory device having high access efficiency, and system provided with interface for data transfer using the same 失效
标题翻译：具有高访问效率的自同步FIFO存储器件，以及具有使用其的数据传输接口的系统
公开(公告)号：US06941434B2
公开(公告)日：2005-09-06
申请号：US10376639
申请日：2003-03-03
申请人： Takuji Uneyama , Manabu Onozaki
发明人： Takuji Uneyama , Manabu Onozaki
IPC分类号： G06F13/38 , G06F5/14 , G06F12/00 , G06F13/00 , G11C7/00
CPC分类号： G06F5/14 , G06F2207/3884
摘要： An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.
摘要翻译：仲裁电路调整来自第一外部设备的写入请求信号的定时和来自第二外部设备的读取请求信号。 RAM根据外部写入请求/读取请求执行数据写入/读取。提供下一状态功能，其具有响应于外部写入请求/读取请求而计算要输入到RAM的写入地址/读取地址的功能，以及准确计数存储在FIFO中的数据的功能。

32. 发明授权

US5373204A Self-timed clocking transfer control circuit 失效
标题翻译：自定时钟传输控制电路
公开(公告)号：US5373204A
公开(公告)日：1994-12-13
申请号：US113824
申请日：1993-08-31
申请人： Tsuyoshi Muramatsu , Manabu Onozaki
发明人： Tsuyoshi Muramatsu , Manabu Onozaki
IPC分类号： G06F13/00 , G06F5/08 , G06F13/36 , G06F15/82 , G11C7/22 , H03K19/096
CPC分类号： G06F5/08 , G11C7/22
摘要： A self-timed clocking transfer control circuit includes a flipflop for storing a transition of a transfer request signal to an L level and outputting an H level signal, an inverter for applying a transfer acknowledge signal to a preceding stage, a 5-input NAND gate, and a second signal output circuit for applying a transfer request signal to a succeeding stage in response to a transition of the output of the 5-input NAND gate to the L level. The 5-input NAND gate does not output the L level unless the transfer request signal from the preceding stage, the output of the flipflop, the transfer acknowledge signal from the succeeding stage, the transfer request signal output by the self-timed clocking transfer control circuit itself, and the prohibition signal are all in the H level. Setting the prohibition signal to the L level, self-synchronous type transfer control can be prohibited. A circuit for generating such a prohibition signal based on a signal for setting an operational mode, a clock signal, and the transfer request signal from the preceding stage may additionally be provided.
摘要翻译：自定时钟传输控制电路包括用于存储转移请求信号转换为L电平并输出H电平信号的触发器，用于向前级施加传送确认信号的反相器，5输入NAND门以及第二信号输出电路，用于响应于5输入NAND门的输出到L电平而将转移请求信号施加到后级。 5输入NAND门不输出L电平，除非来自前一级的传送请求信号，触发器的输出，来自后级的传送确认信号，通过自定时钟传输控制输出的传送请求信号电路本身，禁止信号都处于H电平。将禁止信号设置为L电平，可以禁止自同步型传输控制。可以另外提供用于基于用于设置来自前一级的操作模式，时钟信号和传送请求信号的信号来产生这种禁止信号的电路。

33. 发明授权

US5268902A Data transmission apparatus 失效
标题翻译：数据传输装置
公开(公告)号：US5268902A
公开(公告)日：1993-12-07
申请号：US741625
申请日：1991-08-07
申请人： Manabu Onozaki
发明人： Manabu Onozaki
IPC分类号： G06F15/82 , H04L12/70 , H04J3/24 , H04J3/02
CPC分类号： H04L47/10 , H04L47/266
摘要： A data transmission apparatus includes a word number counting control portion and an arbitration portion. The word number counting control portion generates a transmission acknowledging signal in response to a transmission acknowledging signal received from a first data transmission path. The arbitration portion receives the transmission acknowledging signal from the word number counting control portion and a transmission acknowledging signal from a second data transmission path and applies transmission acknowledging signals to either the first data transmission path or the second data transmission path in the order of arrival. Packets are transmitted to a memory control portion in the succeeding stage from the data transmission path to which the transmission acknowledging signals are applied. Any of the packets includes a flag. The word number counting portion dynamically changes the number of packets to be successively transmitted from the first data transmission path to the memory control portion in response to the flag.
摘要翻译：数据发送装置包括字数计数控制部分和仲裁部分。字数计数控制部分响应于从第一数据传输路径接收的发送确认信号产生发送确认信号。仲裁部分从字数计数控制部分接收发送确认信号和来自第二数据传输路径的发送确认信号，并按照到达顺序将发送确认信号应用于第一数据传输路径或第二数据传输路径。分组从应用发送确认信号的数据传输路径发送到后一级的存储器控制部分。任何数据包都包含一个标志。字数计数部分响应于该标志动态地将从第一数据传输路径连续发送的包的数量改变到存储器控制部分。

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