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    • 32. 发明授权
    • Dual operational mode CML latch
    • 双操作模式CML锁存器
    • US07358787B2
    • 2008-04-15
    • US11307923
    • 2006-02-28
    • Joseph O. MarshJoseph NatonioJames M. Wilson
    • Joseph O. MarshJoseph NatonioJames M. Wilson
    • H03K3/289
    • H03K3/356043
    • A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.
    • 提供了一种双用途电流模式逻辑(“CML”)锁存电路,其包括可操作以接收至少一对差分输入数据信号和至少一个时钟信号的CML锁存器。 CML锁存器可操作以根据输入差分数据信号对的状态产生至少一个输出信号。 模式控制装置可操作以接收模式控制信号以将CML锁存器作为缓冲器或锁存器操作。 以这种方式,当模式控制信号无效时,CML锁存器产生并以由至少一个时钟信号确定的定时锁存输出信号,并且当模式控制信号有效时,CML锁存器产生输出信号,使得 每当差分输入数据信号对的状态改变时,输出信号就会改变。