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31. 发明申请

US20070241395A1 High density memory array having increased channel widths 有权
公开(公告)号：US20070241395A1
公开(公告)日：2007-10-18
申请号：US11811502
申请日：2007-06-11
申请人： Hongmei Wang , Chandra Mouli , Luan Tran
发明人： Hongmei Wang , Chandra Mouli , Luan Tran
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L27/1203 , H01L29/41758 , H01L29/7841 , H01L29/785 , H01L29/7854 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

32. 发明申请

US20070238295A1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20070238295A1
公开(公告)日：2007-10-11
申请号：US11402659
申请日：2006-04-11
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej Sandhu , Luan Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej Sandhu , Luan Tran
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且在第一和第二开口内形成电绝缘材料。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

33. 发明申请

US20060264001A1 Structures with increased photo-alignment margins 有权
标题翻译：具有增加的光对准边缘的结构
公开(公告)号：US20060264001A1
公开(公告)日：2006-11-23
申请号：US11497036
申请日：2006-07-31
申请人： Luan Tran , Bill Stanton
发明人： Luan Tran , Bill Stanton
IPC分类号： H01L21/76 , H01L23/544
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/10894 , H01L27/11517 , Y10S438/942 , Y10S438/947
摘要： Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.
摘要翻译：提供了方法和结构，用于在将间距倍增的互连线与存储器件中的其它导电特征相接触时增加对准边缘。存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。因此，使相邻线路接触和引起电短路的可能性被最小化。此外，相对于阵列区域中的线的一部分以相对于周边的一部分线形成的部分允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。

34. 发明授权

US07118960B2 Selective polysilicon stud growth 有权
标题翻译：选择性多晶硅螺柱生长
公开(公告)号：US07118960B2
公开(公告)日：2006-10-10
申请号：US10933201
申请日：2004-09-02
申请人： Luan Tran
发明人： Luan Tran
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10855 , H01L27/10885
摘要： A memory cell having a bit line contact and a method of manufacturing the memory cell is provided The memory cell may be a 6F2 or smaller memory cell. The bit line contact may have a contact hole bounded by insulating side walls, the contact hole may have a selective, epitaxially grown base layer, may be partially or completely filled with a doped polysilicon plug, and may have a silicide cap. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.
摘要翻译：提供具有位线接触的存储单元和制造存储单元的方法。存储单元可以是6F 2或更小的存储单元。位线接触可以具有由绝缘侧壁界定的接触孔，接触孔可以具有选择性的外延生长的基底层，可以部分地或完全地填充掺杂的多晶硅插塞，并且可以具有硅化物帽。掺杂多晶硅插塞可以具有基本上没有凹面或基本上凸起的上部插塞表面轮廓。类似地，存储节点接触可以包括掺杂的多晶硅插塞，其具有基本上没有凹面或基本上凸起的上插塞表面轮廓。另外，可以提供具有包括多晶硅插头的导电接触的半导体器件。插头可以接触电容器结构。

35. 发明授权

US07115525B2 Method for integrated circuit fabrication using pitch multiplication 有权
公开(公告)号：US07115525B2
公开(公告)日：2006-10-03
申请号：US10934778
申请日：2004-09-02
申请人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
发明人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

36. 发明申请

US20060208282A1 Memory cell arrays 审中-公开
标题翻译：存储单元阵列
公开(公告)号：US20060208282A1
公开(公告)日：2006-09-21
申请号：US11434303
申请日：2006-05-15
申请人： Luan Tran , D. Duncan , Tyler Lowrey , Rob Kerr , Kris Brown
发明人： Luan Tran , D. Duncan , Tyler Lowrey , Rob Kerr , Kris Brown
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10885
摘要： A memory device includes memory cells, bit lines, active areas, and transistors formed in each active area and electrically coupling memory cells to corresponding bit lines. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line may include a first level portion and a second level portion.
摘要翻译：存储器件包括存储器单元，位线，有源区和形成在每个有效区中的晶体管，并将存储单元电耦合到相应的位线。存储器单元可以具有约6F 2的面积，并且位线可以以折叠位线配置耦合到读出放大器。每个位线可以包括第一电平部分和第二电平部分。

37. 发明申请

US20060121712A1 Semiconductor constructions and methods of forming semiconductor constructions 审中-公开
标题翻译：半导体结构和形成半导体结构的方法
公开(公告)号：US20060121712A1
公开(公告)日：2006-06-08
申请号：US11338175
申请日：2006-01-23
申请人： Luan Tran
发明人： Luan Tran
IPC分类号： H01L21/3205
CPC分类号： H01L27/10894 , H01L21/28044 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L27/10873 , H01L27/10888 , H01L27/10891 , H01L29/1041 , H01L29/4916 , H01L29/66537 , H01L29/66553 , H01L29/66583 , H01L29/6659 , H01L29/78 , Y10S438/919 , Y10S438/975
摘要： The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.
摘要翻译：本发明包括具有一对沟道区的半导体结构，所述沟道区具有被铟掺杂并被硼包围的子区。一对晶体管结构位于沟道区上方并由隔离区隔开。晶体管具有比下面的子区域更宽的栅极。本发明还包括半导体结构，其具有在栅极侧壁处具有绝缘间隔物的晶体管结构。每个晶体管结构位于在间隔物下方延伸的一对源/漏区之间。源极/漏极扩展器在仅在晶体管结构中的每一个的一侧上的晶体管结构之下延伸更远的源极/漏极区域。本发明还包括形成半导体结构的方法。

38. 发明申请

US20060046422A1 METHODS FOR INCREASING PHOTO ALIGNMENT MARGINS 有权
标题翻译：增加照片对齐标记的方法
公开(公告)号：US20060046422A1
公开(公告)日：2006-03-02
申请号：US10931771
申请日：2004-08-31
申请人： Luan Tran , Bill Stanton
发明人： Luan Tran , Bill Stanton
IPC分类号： H01L21/76
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/10894 , H01L27/11517 , Y10S438/942 , Y10S438/947
摘要： Abstract of the DisclosureMethods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.
摘要翻译：提供公开的方案和结构的提供用于在将间距倍增的互连线与存储器件中的其它导电特征接触时增加对准边缘。存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。因此，使相邻线路接触和引起电短路的可能性被最小化。此外，相对于阵列区域中的线的一部分以相对于周边的一部分线形成的部分允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。

39. 发明申请

US20050285201A1 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry 有权
公开(公告)号：US20050285201A1
公开(公告)日：2005-12-29
申请号：US11217033
申请日：2005-08-31
申请人： Luan Tran
发明人： Luan Tran
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L21/823481 , H01L27/10894 , H01L27/10897
摘要： Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different. One or more gate lines may be coupled to the respective active areas to provide individual transistors, with the transistors corresponding to the active areas having the different widths having different threshold voltages. In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other.

40. 发明申请

US20050186802A1 Methods of Forming Openings, And Methods of Forming Container Capacitors 有权
标题翻译：形成开口的方法和形成容器电容器的方法
公开(公告)号：US20050186802A1
公开(公告)日：2005-08-25
申请号：US10783843
申请日：2004-02-20
申请人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
发明人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
IPC分类号： H01L21/02 , H01L21/033 , H01L21/302 , H01L21/311 , H01L21/461 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L29/76
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

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