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31. 发明申请

US20070103350A1 Methods and apparatus for testing an integrated circuit 失效
标题翻译：用于测试集成电路的方法和装置
公开(公告)号：US20070103350A1
公开(公告)日：2007-05-10
申请号：US11272589
申请日：2005-11-10
申请人： Louis Hsu , Jack Mandelman , Joseph Marsh , Steven Zier
发明人： Louis Hsu , Jack Mandelman , Joseph Marsh , Steven Zier
IPC分类号： H03M1/10
CPC分类号： H03M1/1076
摘要： In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供一种测试模拟电路的方法。该方法包括（1）向模拟电路提供一种适合于使模拟电路在测试期间像逻辑门一样起作用的屏蔽电路; 和（2）将数字信号施加到模拟电路以在晶片级测试模拟电路，以便检测模拟电路的一个或多个部件中的缺陷。提供了许多其他方面。

32. 发明申请

US20070099326A1 eFuse and methods of manufacturing the same 有权
标题翻译： eFuse及其制造方法
公开(公告)号：US20070099326A1
公开(公告)日：2007-05-03
申请号：US11266740
申请日：2005-11-03
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是eFuse，包括（1）衬底的绝缘氧化物层上方的半导体层; （2）形成在半导体层中的二极管; 和（3）二极管上形成的硅化物层。提供了许多其他方面。

33. 发明申请

US20070057325A1 Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures 有权
标题翻译：具有封装的栅电极的半导体FinFET结构和用于形成这种半导体FinFET结构的方法
公开(公告)号：US20070057325A1
公开(公告)日：2007-03-15
申请号：US11225654
申请日：2005-09-13
申请人： Louis Hsu , Jack Mandelman
发明人： Louis Hsu , Jack Mandelman
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.
摘要翻译：其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。

34. 发明申请

US20070018239A1 Sea-of-fins structure on a semiconductor substrate and method of fabrication 审中-公开
标题翻译：半导体衬底上的海鳍结构和制造方法
公开(公告)号：US20070018239A1
公开(公告)日：2007-01-25
申请号：US11185646
申请日：2005-07-20
申请人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
发明人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
IPC分类号： H01L29/76
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L27/1211 , H01L29/66795 , H01L29/66803 , H01L29/785 , Y10S977/734 , Y10S977/742 , Y10S977/749 , Y10S977/815 , Y10S977/955
摘要： A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.
摘要翻译：一种半导体器件和半导体器件的制造方法，其中所述方法包括在衬底上形成多个用于定制鳍状场效应晶体管（FinFET）器件形成的平坦化翅片体; 在所述多个翅片体中的每一个周围形成氮化物间隔物; 在每个翅片体之间形成隔离区域; 并用保护膜涂覆多个翅片体，氮化物间隔物和隔离区域。制造的半导体器件适用于定制应用中作为定制的半导体器件。

35. 发明申请

US20080050891A1 COPLANAR SILICON-ON-INSULATOR (SOI) REGIONS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHODS OF MAKING THE SAME 有权
标题翻译：共晶硅绝缘体（SOI）区域的不同晶体取向及其制备方法
公开(公告)号：US20080050891A1
公开(公告)日：2008-02-28
申请号：US11929106
申请日：2007-10-30
申请人： LOUIS HSU , Jack Mandelman
发明人： LOUIS HSU , Jack Mandelman
IPC分类号： H01L21/20
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了半导体器件制造的第一种方法。第一种方法包括以下步骤：（1）提供衬底; 和（2）在基板上形成具有第一晶体取向的第一绝缘体上硅（SOI）区域，具有第二晶体取向的第二SOI区域和具有第三晶体取向的第三SOI区域。第一，第二和第三SOI区域是共面的。提供了许多其他方面。

36. 发明申请

US20080050890A1 HYBRID ORIENTED SUBSTRATES AND CRYSTAL IMPRINTING METHODS FOR FORMING SUCH HYBRID ORIENTED SUBSTRATES 失效
标题翻译：用于形成这种混合基板的混合基板和晶体印刷方法
公开(公告)号：US20080050890A1
公开(公告)日：2008-02-28
申请号：US11928456
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.
摘要翻译：一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。体硅区域各自定向为具有第三晶体取向。还提供了形成SOI区域和体硅区域的镶嵌或印刷方法。

37. 发明申请

US20080034335A1 Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering 有权
标题翻译：结合具有减少的结电容和漏极诱导的阻挡层的半导体器件结构的设计结构
公开(公告)号：US20080034335A1
公开(公告)日：2008-02-07
申请号：US11875013
申请日：2007-10-19
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： G11C29/54
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：用于设计，制造或测试设计的机器可读介质中体现的设计结构。该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

38. 发明申请

US20070246752A1 SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED JUNCTION CAPACITANCE AND DRAIN INDUCED BARRIER LOWERING AND METHODS FOR FABRICATING SUCH DEVICE STRUCTURES AND FOR FABRICATING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 失效
标题翻译：具有降低的接合电容和漏极诱发障碍物下降的半导体器件结构以及用于制造这种器件结构和用于制造半导体绝缘体衬底的方法
公开(公告)号：US20070246752A1
公开(公告)日：2007-10-25
申请号：US11379655
申请日：2006-04-21
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/66545 , H01L29/51 , H01L29/513 , H01L29/66636 , H01L29/66772 , H01L29/78603 , Y10S438/96
摘要： Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.
摘要翻译：具有减小的结电容和漏极引起的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。制造方法包括修改介电层的区域以具有较低的介电常数。

39. 发明申请

US20070202637A1 BODY CAPACITOR FOR SOI MEMORY 有权
标题翻译：用于SOI存储器的身体电容器
公开(公告)号：US20070202637A1
公开(公告)日：2007-08-30
申请号：US11742147
申请日：2007-04-30
申请人： Jack Mandelman , Louis Hsu , Rajiv Joshi
发明人： Jack Mandelman , Louis Hsu , Rajiv Joshi
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/108 , H01L27/10832 , H01L27/10858 , H01L27/1203 , H01L29/94
摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.
摘要翻译：提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠在本发明中获得的精确控制并且不受对准公差的影响。与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

40. 发明申请

US20070166890A1 PFETS and methods of manufacturing the same 失效
标题翻译： PFETS及其制造方法
公开(公告)号：US20070166890A1
公开(公告)日：2007-07-19
申请号：US11335763
申请日：2006-01-19
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： H01L21/84
CPC分类号： H01L29/66742 , H01L29/165 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate. The at least one composite source/drain diffusion region is adapted to cause a strain in the gate channel region. Further, significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了在衬底上制造PFET的第一种方法。第一种方法包括以下步骤：（1）在衬底上形成具有第一厚度的PFET的栅极沟道区; 和（2）在衬底上形成具有大于第一厚度的第二厚度的PFET的至少一个复合源极/漏极扩散区域。至少一个复合源极/漏极扩散区域适于在栅极沟道区域引起应变。此外，显着地所有的至少一个复合源极/漏极扩散区域在PFET的栅极的底表面之下。提供了许多其他方面。

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