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31. 发明申请

US20090216957A1 Managing the storage of data in coherent data stores 有权
标题翻译：管理连贯数据存储中的数据存储
公开(公告)号：US20090216957A1
公开(公告)日：2009-08-27
申请号：US12071504
申请日：2008-02-21
申请人： Nicolas Chaussade , Stephane Eric Sebastien Brochier
发明人： Nicolas Chaussade , Stephane Eric Sebastien Brochier
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F12/0811 , G06F12/084 , G06F12/0868 , G06F12/0891 , G06F2212/1016
摘要： A data processing apparatus is disclosed that comprises: at least one processor; at least one data store for storing data processed by said at least one processor; a shared data store for storing data processed by said at least one processor and at least one further device; and coherency control circuitry responsive to a write request from said at least one further device to determine if data related to an address targeted by said write request is stored in said at least one data store, and if it is forcing an eviction of said stored data from said at least one data store to said shared data store prior to performing said write to said shared data store; wherein said data is stored in said at least one data store in conjunction with an indicator indicating if said stored data is consistent with data stored in a corresponding address in a further data store, and said stored data is evicted whether said stored data is indicated as being consistent or inconsistent.
摘要翻译：公开了一种数据处理装置，包括：至少一个处理器; 用于存储由所述至少一个处理器处理的数据的至少一个数据存储器; 共享数据存储器，用于存储由所述至少一个处理器处理的数据和至少一个另外的设备; 以及响应于来自所述至少一个另外的设备的写请求的相关性控制电路，以确定与所述写请求所针对的地址相关的数据是否存储在所述至少一个数据存储器中，并且如果它强制驱逐所述存储的数据在对所述共享数据存储器执行所述写入之前，从所述至少一个数据存储器到所述共享数据存储器; 其中所述数据与指示所述存储的数据是否与存储在另一个数据存储器中的对应地址中的数据一致的指示符存储在所述至少一个数据存储器中，并且所述存储的数据被驱逐是否所述存储的数据被指示为一致或不一致。

32. 发明申请

US20090210595A1 Data transfer between devices within an integrated circuit 有权
标题翻译：集成电路内的器件之间的数据传输
公开(公告)号：US20090210595A1
公开(公告)日：2009-08-20
申请号：US12320718
申请日：2009-02-03
申请人： Nicolas Chaussade
发明人： Nicolas Chaussade
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , H03M7/46
摘要： An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in place of that repeating data word itself. The receiving device can then form the repeating pattern of data words in response to receipt of the representation. This reduces the bandwidth consumed upon the interconnect 16.
摘要翻译：提供了集成电路2，其包括用于经由互连16进行通信的多个设备4,6,8,10,12,14。发送设备18包括表示使用重复数据字的表示的边带信号，代替该重复数据字的表示重复数据字本身。然后，响应于接收到表示，接收设备可以形成数据字的重复模式。这减少了互连16上消耗的带宽。

33. 发明申请

US20090182949A1 Cache eviction 有权
标题翻译：缓存驱逐
公开(公告)号：US20090182949A1
公开(公告)日：2009-07-16
申请号：US12382449
申请日：2009-03-17
申请人： Florent Begon , Philippe Luc , Elodie Charra , Nicolas Chaussade
发明人： Florent Begon , Philippe Luc , Elodie Charra , Nicolas Chaussade
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0859 , Y02D10/13
摘要： A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2) transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.
摘要翻译：一种方法和数据处理装置，包括具有多个数据条目的高速缓存; 驱逐缓冲器，包括信息部分和数据部分; 以及驱逐逻辑，用于将与所述多个数据条目中的第一数据条目相关联的信息从所述高速缓存传送到所述信息部分，并且参考所述信息来确定所述多个数据条目中的第一条数据条目是否应通过检查被写入存储器信息。如果确定数据输入应被写入存储器，驱逐逻辑（1）将信息从驱逐缓冲器传送到与存储器耦合的总线，（2）传送多个数据条目中的第一个的数据从高速缓存到驱逐缓冲器的数据部分，（3）将与多个数据条目中的第二数据条目相关联的信息从高速缓存传送到驱逐缓冲器的关联部分，使得由驱逐的数据部分存储的数据缓冲器对应于多个数据条目中的第一个，并且由驱逐缓冲器的数据部分存储的信息对应于多个数据条目中的第二数据条目，并且（4）传送由驱逐缓冲器的数据部分存储的数据到公共汽车这种方法提供了一种低功耗，高性能的处理驱逐要求的技术。

34. 发明授权

US08578139B2 Checkpointing long latency instruction as fake branch in branch prediction mechanism 有权
标题翻译：在分支预测机制中检查长延时指令为假分支
公开(公告)号：US08578139B2
公开(公告)日：2013-11-05
申请号：US12805567
申请日：2010-08-05
申请人： Nicolas Chaussade , Florent Begon , Mélanie Emanuelle Lucie Teyssier , Rémi Teyssier , Jocelyn Francois Orion Jaubert
发明人： Nicolas Chaussade , Florent Begon , Mélanie Emanuelle Lucie Teyssier , Rémi Teyssier , Jocelyn Francois Orion Jaubert
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30145 , G06F9/3842 , G06F9/3863
摘要： A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction.
摘要翻译：提供数据处理装置和数据处理方法。该数据处理装置包括被配置为执行程序指令序列的执行电路。检查点电路被配置为识别程序指令序列中的预定类型的指令的实例，并且存储与该实例相关联的检查点信息。检查点信息在执行预定类型的指令的该实例之前识别数据处理装置的状态，其中预定类型的指令具有期望的长完成延迟。如果执行电路由于发生预定事件而没有完成预定类型的指令的实例的执行，则数据处理装置被配置为参照检查点信息恢复数据处理装置的状态，使得然后，执行电路被配置为在预定类型的指令的那个情况下重新开始执行程序指令的序列。

35. 发明授权

US07941608B2 Cache eviction 有权
标题翻译：缓存驱逐
公开(公告)号：US07941608B2
公开(公告)日：2011-05-10
申请号：US12382449
申请日：2009-03-17
申请人： Florent Begon , Philippe Luc , Elodie Charra , Nicolas Chaussade
发明人： Florent Begon , Philippe Luc , Elodie Charra , Nicolas Chaussade
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0859 , Y02D10/13
摘要： A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2) transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.
摘要翻译：一种方法和数据处理装置，包括具有多个数据条目的高速缓存; 驱逐缓冲器，包括信息部分和数据部分; 以及驱逐逻辑，用于将与所述多个数据条目中的第一数据条目相关联的信息从所述高速缓存传送到所述信息部分，并且参考所述信息来确定所述多个数据条目中的第一条数据条目是否应通过检查被写入存储器信息。如果确定数据输入应被写入存储器，驱逐逻辑（1）将信息从驱逐缓冲器传送到与存储器耦合的总线，（2）传送多个数据条目中的第一个的数据从高速缓存到驱逐缓冲器的数据部分，（3）将与多个数据条目中的第二数据条目相关联的信息从高速缓存传送到驱逐缓冲器的关联部分，使得由驱逐的数据部分存储的数据缓冲器对应于多个数据条目中的第一个，并且由驱逐缓冲器的数据部分存储的信息对应于多个数据条目中的第二数据条目，并且（4）传送由驱逐缓冲器的数据部分存储的数据到公共汽车这种方法提供了一种低功耗，高性能的处理驱逐要求的技术。

36. 发明授权

US07934029B2 Data transfer between devices within an integrated circuit 有权
标题翻译：集成电路内的器件之间的数据传输
公开(公告)号：US07934029B2
公开(公告)日：2011-04-26
申请号：US12320718
申请日：2009-02-03
申请人： Nicolas Chaussade
发明人： Nicolas Chaussade
IPC分类号： G06F13/12 , H03M7/38
CPC分类号： G06F13/4022 , H03M7/46
摘要： An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in place of that repeating data word itself. The receiving device can then form the repeating pattern of data words in response to receipt of the representation. This reduces the bandwidth consumed upon the interconnect 16.
摘要翻译：提供了集成电路2，其包括用于经由互连16进行通信的多个设备4,6,8,10,12,14。发送设备18包括表示使用重复数据字的表示的边带信号，代替该重复数据字的表示重复数据字本身。然后，响应于接收到表示，接收设备可以形成数据字的重复模式。这减少了互连16上消耗的带宽。

37. 发明授权

US07533241B2 Variable size cache memory support within an integrated circuit 有权
标题翻译：集成电路内的可变大小缓存内存支持
公开(公告)号：US07533241B2
公开(公告)日：2009-05-12
申请号：US11634253
申请日：2006-12-06
申请人： Florent Begon , Vladimir Vasekin , Andrew Christophe Rose , Nicolas Chaussade
发明人： Florent Begon , Vladimir Vasekin , Andrew Christophe Rose , Nicolas Chaussade
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0802 , G06F2212/601
摘要： An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.
摘要翻译：集成电路2设置有高速缓冲存储器6和高速缓存控制器10，高速缓存控制器10经由高速缓存存储器接口8耦合到高速缓存存储器6.高速缓存控制器支持不同的高速缓冲存储器大小。高速缓存存储器6包括响应于高速缓存存储器大小信号的掩蔽逻辑14，以形成用于访问高速缓冲存储器6的掩蔽地址值。高速缓存控制器10可以是处理器核心4的一部分，处理器核心4可以在其设计中硬化并且能够以应对可变高速缓冲存储器大小，因为屏蔽逻辑14被提供在处理器核心4的硬化外围之外的高速缓冲存储器6内。

38. 发明申请

US20080168233A1 Cache circuitry, data processing apparatus and method for handling write access requests 失效
标题翻译：缓存电路，数据处理装置和处理写访问请求的方法
公开(公告)号：US20080168233A1
公开(公告)日：2008-07-10
申请号：US11651620
申请日：2007-01-10
申请人： Philippe Luc , Florent Begon , Elodie Charra , Nicolas Chaussade
发明人： Philippe Luc , Florent Begon , Elodie Charra , Nicolas Chaussade
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0897 , G06F12/1027
摘要： Cache circuitry, a data processing apparatus including such cache circuitry, and a method of handling write requests within cache circuitry, are provided. The cache circuitry has a plurality of slots, with each slot arranged to store attributes associated with a pending access request. A record of identifiers that are available to associate with pending access requests is maintained, and control circuitry is responsive to an access request issued by a device to accept that access request as a pending access request by allocating one of the slots to that access request, obtaining one of said identifiers from the record to associate with that access request, and causing the attributes associated with that access request to be stored in the allocated slot along with the obtained identifier. A check procedure is performed to determine, for each pending access request, whether that access request is allowed to proceed. For a speculative pending write access request that is determined to be allowed to proceed, the attributes associated with that access request and the identifier associated with that access request are transferred from the allocated slot to a write entry within a write access buffer, after which the allocated slot is freed for allocation to a subsequent access request. When a speculative confirmed signal is then received from the device specifying that identifier, the write access buffer outputs the attributes from the write entry to store circuitry used to complete the access request. This provides a very efficient mechanism for handling speculative write accesses within a cache.
摘要翻译：提供了缓存电路，包括这种高速缓存电路的数据处理设备，以及处理高速缓存电路内的写请求的方法。高速缓存电路具有多个时隙，每个时隙被布置成存储与待处理的接入请求相关联的属性。维持可用于与未决访问请求相关联的标识符的记录，并且控制电路响应于由设备发出的访问请求，以将该访问请求作为未决访问请求来分配其中一个时隙给该访问请求，从所述记录中获取所述标识符之一以与所述访问请求相关联，并且将与所述访问请求相关联的属性与所获得的标识符一起存储在所分配的时隙中。执行检查过程，以确定对于每个未决访问请求，是否允许该访问请求继续进行。对于被确定为允许继续进行的推测性待决写入访问请求，与该访问请求相关联的属性和与该访问请求相关联的标识符从分配的时隙转移到写访问缓冲器内的写入条目，之后分配的时隙被释放以分配给后续的访问请求。当从指定该标识符的设备接收到推测确认的信号时，写入访问缓冲器从写入条目输出属性以存储用于完成访问请求的存储电路。这提供了一种处理高速缓存中的推测性写入访问的非常有效的机制。

39. 发明申请

US20080147921A1 Data transfer between a master and slave 有权
标题翻译：主机与从机之间的数据传输
公开(公告)号：US20080147921A1
公开(公告)日：2008-06-19
申请号：US11979361
申请日：2007-11-01
申请人： Nicolas Chaussade , Pierre Michel Broyer , Phillipe Luc
发明人： Nicolas Chaussade , Pierre Michel Broyer , Phillipe Luc
IPC分类号： G06F1/12
CPC分类号： G06F13/4291
摘要： A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configured to output signals that are different to each other.
摘要翻译：一种数据处理装置，包括至少一个启动器，其可操作以经由总线与至少一个接收者通信; 所述至少一个起动器包括用于向所述总线发送数据的输出端口和用于从所述总线接收数据的输入端口; 所述数据处理装置还包括启动器时钟信号发生器，启动器输出使能信号发生器和启动器输入使能信号发生器，所述启动器由所述启动器时钟信号计时; 所述输出端口由所述启动器输出使能信号计时，使得所述输出端口可操作以响应于具有第一预定电平的所述启动器输出使能信号而将数据断言在所述总线上的写通道，并且所述输入端口可操作以锁存数据响应于所述启动器输入使能信号具有第二预定电平，在所述总线上的读通道上接收; 其中所述启动器输出使能信号发生器和启动器输入使能信号发生器被配置为输出彼此不同的信号。

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