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31. 发明授权

US06385694B1 High performance load instruction management via system bus with explicit register load and/or cache reload protocols 有权
标题翻译：通过具有显式寄存器加载和/或缓存重新加载协议的系统总线进行高性能加载指令管理
公开(公告)号：US06385694B1
公开(公告)日：2002-05-07
申请号：US09340079
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0859
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译：一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。本发明可以应用于例如指令，操作数数据和翻译高速缓存。

32. 发明授权

US06970976B1 Layered local cache with lower level cache optimizing allocation mechanism 有权
标题翻译：分层本地缓存，具有较低级别的缓存优化分配机制
公开(公告)号：US06970976B1
公开(公告)日：2005-11-29
申请号：US09340074
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F12/08 , G06F12/10 , G06F12/14
CPC分类号： G06F12/0897 , G06F12/0831 , G06F12/0859 , G06F12/1027
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (Li) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译：一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。然后可能不精确地重新加载上层（Li）高速缓存（上级缓存也可能不精确地用存储指令重新加载）。低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。本发明可以应用于例如指令，操作数数据和翻译高速缓存。

33. 发明授权

US06823471B1 Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem 失效
标题翻译：一种通过可重配置散列存储子系统在数据处理系统内提供高可用性的方法
公开(公告)号：US06823471B1
公开(公告)日：2004-11-23
申请号：US09364281
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1100
CPC分类号： G06F11/20
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
摘要翻译：处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。执行资源，数据存储和指令排序单元中的至少一个由具有用于处理多个数据流中的相应一个的类似功能的多个硬件分区来实现。如果在特定硬件分区中检测到错误，则分配给该硬件分区的数据流被重新分配给多个硬件分区中的另一个，从而防止其中一个硬件分区中的错误导致灾难性故障。

34. 发明授权

US06446165B1 Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) 失效
标题翻译：具有HSA（散列存储架构）的数据处理系统中的依赖于地址的缓存行为
公开(公告)号：US06446165B1
公开(公告)日：2002-09-03
申请号：US09364287
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0811
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
摘要翻译：处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。存储由执行单元使用的数据的高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据，并且实现多种缓存行为。不同的缓存行为可以包括不同的内存更新策略，不同的一致性协议，不同的预取行为以及不同的缓存行替换策略。

35. 发明授权

US06473833B1 Integrated cache and directory structure for multi-level caches 失效
标题翻译：多级缓存的集成缓存和目录结构
公开(公告)号：US06473833B1
公开(公告)日：2002-10-29
申请号：US09364570
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , James Stephen Fields, Jr. , Lakshminarayana Baba Arimilli
发明人： Ravi Kumar Arimilli , Leo James Clark , James Stephen Fields, Jr. , Lakshminarayana Baba Arimilli
IPC分类号： G06F1200
CPC分类号： G06F12/0897
摘要： A method of operating a multi-level memory hierarchy of a computer system and an apparatus embodying the method, wherein multiple levels of storage subsystems are used to improve the performance of the computer system, each next higher level generally having a faster access time, but a smaller amount of storage. Values within a level are indexed by a directory that provides an indexing of information relating the values in that level to the next lower level. In a preferred embodiment of the invention, the directories for the various levels of storage are contained within the next higher level, providing a faster access to the directory information. Cache memories used as the highest levels of storage, and one or more sets are allocated out of that cache memory for containing a directory of the next lower level of storage. An address comparator which is used to compare entries in a directory to address values is directly coupled to the set or sets used for the directory, reducing the time needed to compare addresses in determining whether an address is present in the cache.
摘要翻译：一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中使用多级存储子系统来提高计算机系统的性能，每个下一级别通常具有更快的访问时间，但是更少的存储空间。级别中的值由一个目录索引，该目录提供与该级别中的值相关联的信息与下一级别的索引。在本发明的优选实施例中，用于各种级别的存储的目录被包含在下一较高级别内，从而提供对目录信息的更快访问。高速缓冲存储器被用作最高级别的存储器，并且从该高速缓存存储器中分配一个或多个集合，用于包含下一较低级存储的目录。用于将目录中的条目与地址值进行比较的地址比较器直接耦合到用于目录的集合或集合，减少了在确定地址是否存在于高速缓存中时比较地址所需的时间。

36. 发明授权

US06516404B1 Data processing system having hashed architected processor facilities 失效
标题翻译：数据处理系统散布了架构化的处理器设备
公开(公告)号：US06516404B1
公开(公告)日：2003-02-04
申请号：US09364283
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/384 , G06F12/06 , G06F12/0846
摘要： A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
摘要翻译：具有散列和分区寄存器文件的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和耦合到执行单元的多个寄存器。多个寄存器被划分成多个组，使得每个组中的寄存器可以仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据。

37. 发明授权

US06463507B1 Layered local cache with lower level cache updating upper and lower level cache directories 失效
标题翻译：具有较低级别缓存的分层本地缓存更新上下级缓存目录
公开(公告)号：US06463507B1
公开(公告)日：2002-10-08
申请号：US09340082
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831 , G06F12/1027
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译：一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。本发明可以应用于例如指令，操作数数据和翻译高速缓存。

38. 发明授权

US06606666B1 Method and system for controlling information flow between a producer and a buffer in a high frequency digital system 失效
标题翻译：用于控制高频数字系统中的制造商和缓冲器之间的信息流的方法和系统
公开(公告)号：US06606666B1
公开(公告)日：2003-08-12
申请号：US09436962
申请日：1999-11-09
申请人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
发明人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
IPC分类号： G06F1516
CPC分类号： H04L47/39 , H04L47/10 , H04L49/90
摘要： An information handling system includes a producer that outputs packets, a buffer that receives packets from the producer, buffers the packets, and eventually outputs the packets, and a control unit that controls the flow of packets from the producer to the buffer. The control unit receives as inputs a producer output indication indicating that the producer has output a packet to the buffer and a buffer output indication indicating that the buffer has output a packet. Based upon a capacity of the buffer, a number of the producer output indications, a number of buffer output indications, and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. In response to a determination that the producer can output a packet without packet loss, the control unit outputs a grant message to the producer indicating that the producer is permitted to output a packet.
摘要翻译：信息处理系统包括输出分组的生成器，从生成器接收分组的缓冲器，缓冲分组，最终输出分组，以及控制单元，控制从生成器到缓冲器的分组流。控制单元作为输入接收指示生成者已经向缓冲器输出分组的生成器输出指示和指示缓冲器已经输出分组的缓冲器输出指示。基于缓冲器的容量，多个生成器输出指示，多个缓冲器输出指示以及在控制单元的反馈等待时间内向生成器输出的许多准许消息，控制单元是否可以输出一个没有数据包丢失的数据包。响应于确定生产者可以输出没有分组丢失的分组，控制单元向生产者输出授权消息，指示生产者被允许输出分组。

39. 发明授权

US06598086B1 Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer 失效
标题翻译：用于通过中间缓冲器控制从生产者到缓冲消费者的高频数字系统中的信息流的方法和系统
公开(公告)号：US06598086B1
公开(公告)日：2003-07-22
申请号：US09436961
申请日：1999-11-09
申请人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
发明人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
IPC分类号： G06F1516
CPC分类号： H04L47/527 , H04L47/28 , H04L47/50 , H04L49/90
摘要： An information handling system includes a plurality of sequentially connected units including a first unit, a second unit and a third unit. Packets of information flow from the first unit directly to the second unit and then to the third unit, and each of the plurality of units provides a respective dynamic output indication indicating if that unit output a packet. The information handling system further includes a control unit that determines, utilizing all of the plurality of dynamic output indications, packet buffering capacities of the plurality of units, and guaranteed packet flows between adjacent ones of the plurality of units, if the first unit can output a packet directly to the second unit without packet loss. In response to this determination, the control unit outputs a control signal to the first unit.
摘要翻译：信息处理系统包括多个依次连接的单元，包括第一单元，第二单元和第三单元。信息包从第一单元直接传输到第二单元，然后流向第三单元，并且多个单元中的每个单元提供指示该单元是否输出分组的相应的动态输出指示。所述信息处理系统还包括：控制单元，其确定利用所述多个动态输出指示中的所有多个单元的分组缓冲能力以及所述多个单元中的相邻单元之间的保证的分组流，如果所述第一单元可以输出一个数据包直接连到第二个单元没有丢包。响应于该确定，控制单元向第一单元输出控制信号。

40. 发明授权

US06604145B1 Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path 失效
标题翻译：用于通过中间缓冲器和共享数据路径来控制从生产者到缓冲用户的高频数字系统中的信息流的方法和系统
公开(公告)号：US06604145B1
公开(公告)日：2003-08-05
申请号：US09436963
申请日：1999-11-09
申请人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
发明人： Robert Henry Bell, Jr. , Robert Alan Cargnoni , Leo James Clark , William John Starke
IPC分类号： G06F1516
CPC分类号： H04L47/10 , H04L47/27 , H04L47/39
摘要： An information handling system includes a plurality of producers that output packets of information, at least one consumer of the packets, and an information pipeline coupling the consumer and at least a particular producer among the plurality of producers. The information pipeline includes a shared resource having a bandwidth shared by multiple of the plurality of producers. The information handling system further includes a control unit that regulates packet output of the particular producer and that receives as inputs a producer output indication indicating that the particular producer output a packet and a shared resource input indication indicating that a packet output by the particular producer has been accepted by the shared resource for transmission to the consumer. Based upon these inputs, a number of grant messages output to the particular producer within a feedback latency of the control unit, and a portion of the bandwidth allocated to the particular producer, the control unit whether the particular producer can output a packet without packet loss. In response to a determination that the particular producer can output a packet without packet loss, the control unit outputs a grant message to the particular producer indicating that the particular producer is permitted to output a packet.
摘要翻译：信息处理系统包括输出信息分组的多个生成器，分组的至少一个消费者，以及耦合消费者和多个生产者中的至少特定生产者的信息流水线。信息流水线包括具有由多个生产者中的多个共享的带宽的共享资源。信息处理系统还包括控制单元，其调节特定生产者的分组输出并且接收指示特定生成者输出分组的生成器输出指示和指示由特定生产者输出的分组的共享资源输入指示由共享资源接受传输给消费者。基于这些输入，在控制单元的反馈等待时间内向特定生产者输出的许多授权消息以及分配给特定生产者的带宽的一部分，控制单元特定生产者是否可以输出分组而不丢包。响应于确定特定制作者可以输出没有分组丢失的分组，控制单元向特定制作者输出指示特定制作者被允许输出分组的授权消息。

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