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31. 发明授权

US06943401B1 Flash memory cell with drain and source formed by diffusion of a dopant from a silicide 有权
标题翻译：具有漏极和源极的闪存单元由掺杂剂从硅化物扩散形成
公开(公告)号：US06943401B1
公开(公告)日：2005-09-13
申请号：US10661720
申请日：2003-09-11
申请人： Shenqing Fang
发明人： Shenqing Fang
IPC分类号： H01L29/788
CPC分类号： H01L29/0847 , H01L21/28273 , H01L29/0891 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： The present invention is a flash memory manufacturing process that facilitates efficient fabrication of a flash memory cell. In one embodiment, a silicide (e.g., CoSi) is utilized as a diffusion source. A layer of silicide is deposited over a source area and drain area. The dopant is implanted into the CoSi and diffuse out conformably along CoSi-Si interface at a relatively low temperature. The low temperature diffusion facilitates fabrication of a Flash core cell with a very shallow source/drain junction, and as a result a robust DIBL. The present invention also facilitates fabrication of memory cells with smaller spacers and shorter gate length.
摘要翻译：本发明是一种有助于快速存储单元的制造的闪存制造工艺。在一个实施例中，使用硅化物（例如CoSi）作为扩散源。一层硅化物沉积在源区和漏区上。将掺杂剂注入到CoSi中，并在较低的温度下沿着CoSi-Si界面顺应扩散。低温扩散有助于制造具有非常浅的源极/漏极结的闪存核心单元，并且因此具有鲁棒的DIBL。本发明还有利于具有较小间隔物和较短栅极长度的存储器单元的制造。

32. 发明授权

US06927129B1 Narrow wide spacer 有权
标题翻译：狭窄的间距
公开(公告)号：US06927129B1
公开(公告)日：2005-08-09
申请号：US10821312
申请日：2004-04-08
申请人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
发明人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L29/6656 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： A method for fabricating a semiconductor device. Specifically, A method of manufacturing a semiconductor device comprising: depositing a first oxide layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comprising a gate stack, a source side sidewall and a drain side sidewall; etching the first oxide layer wherein a portion of the first oxide layer remains on the source side sidewall and on the drain side sidewall of the periphery transistor and on the source side sidewall and on the drain side sidewall of the core transistor; etching the first oxide layer from the source side sidewall of the core transistor; depositing a second oxide layer over the periphery transistor and the core transistor; and etching the second oxide layer wherein a portion of the second oxide layer remains on the first oxide layer formed on the source side sidewall and on the drain side sidewall of the periphery transistor and wherein the second oxide layer remains on the source side sidewall and on the drain side sidewall of the core transistor.
摘要翻译：一种半导体器件的制造方法。具体地说，一种制造半导体器件的方法，包括：在包括栅极堆叠，漏极侧壁和源极侧壁的外围晶体管上沉积第一氧化物层，以及包括栅极堆叠，源极侧壁和排水侧壁蚀刻第一氧化物层，其中第一氧化物层的一部分保留在外围晶体管的源极侧壁和漏极侧壁上，并且在芯晶体管的源极侧壁和漏极侧侧壁上残留; 从芯晶体管的源极侧壁蚀刻第一氧化物层; 在外围晶体管和芯晶体管上沉积第二氧化物层; 以及蚀刻所述第二氧化物层，其中所述第二氧化物层的一部分保留在形成在所述外围晶体管的源极侧壁和漏极侧壁上的第一氧化物层上，并且其中所述第二氧化物层保留在所述源侧侧壁上，芯晶体管的漏极侧壁。

33. 发明授权

US08598646B2 Non-volatile FINFET memory array and manufacturing method thereof 有权
标题翻译：非易失性FINFET存储器阵列及其制造方法
公开(公告)号：US08598646B2
公开(公告)日：2013-12-03
申请号：US13006339
申请日：2011-01-13
申请人： Chun Chen , Shenqing Fang
发明人： Chun Chen , Shenqing Fang
IPC分类号： H01L27/105
CPC分类号： H01L21/28282 , H01L21/76224 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/66833
摘要： An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.
摘要翻译：一种电子器件包括具有半导体表面的衬底，具有通过存储单元区域和选择栅极区域沿第一方向共同延伸的多个鳍式突起。电子设备还包括设置在突起之间的空间中的电介质隔离材料。在电子设备中，存储单元区域中的介质隔离材料的高度小于存储单元区域中的突起的高度，并且选择栅极区域中的介电隔离材料的高度大于或等于突起在选择栅极区域的高度。电子设备还包括设置在存储单元区域内的衬底上的栅极特征以及突出部分和介电隔离材料上的选择栅极区域，其中栅极特征在横向于第一方向的第二方向上共同延伸。

34. 发明授权

US07951704B2 Memory device peripheral interconnects and method of manufacturing 有权
标题翻译：存储器件外设互连和制造方法
公开(公告)号：US07951704B2
公开(公告)日：2011-05-31
申请号：US12512960
申请日：2009-07-30
申请人： Shenqing Fang , Wenmei Li
发明人： Shenqing Fang , Wenmei Li
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/76816 , H01L23/485 , H01L27/1052 , H01L27/11529 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.
摘要翻译：在一个实施例中，集成电路存储器件包括衬底和连续地设置在衬底上的第一和第二级间介电层。外围设备中的一个或多个触点延伸穿过第一层间电介质层到相应的部件。一个或多个通孔和多个虚拟通孔延伸穿过周边区域中的第二层间电介质层。一个或多个外围通孔中的每一个延伸到相应的外围触点。外围的虚拟通孔位于外围通孔附近。

35. 发明授权

US07867899B2 Wordline resistance reduction method and structure in an integrated circuit memory device 有权
标题翻译：集成电路存储器件中的字线电阻降低方法和结构
公开(公告)号：US07867899B2
公开(公告)日：2011-01-11
申请号：US12111886
申请日：2008-04-29
申请人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
发明人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
IPC分类号： H01L21/44 , H01L21/02
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

36. 发明授权

US07851306B2 Method for forming a flash memory device with straight word lines 有权
标题翻译：用于形成具有直线字线的闪速存储器件的方法
公开(公告)号：US07851306B2
公开(公告)日：2010-12-14
申请号：US12327641
申请日：2008-12-03
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

37. 发明申请

US20080265301A1 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US20080265301A1
公开(公告)日：2008-10-30
申请号：US11796582
申请日：2007-04-26
申请人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillips Jones , Mark Chang , Minh-Van Ngo
发明人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillips Jones , Mark Chang , Minh-Van Ngo
IPC分类号： H01L29/788 , H01L21/3205
CPC分类号： H01L21/28282 , H01L27/11568
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。然后在核心单元之间完全或部分蚀刻捕获层。去除非保形膜。并形成顶部氧化物。如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

38. 发明授权

US09412598B2 Edge rounded field effect transistors and methods of manufacturing 有权
标题翻译：边缘圆形场效应晶体管和制造方法
公开(公告)号：US09412598B2
公开(公告)日：2016-08-09
申请号：US12973756
申请日：2010-12-20
申请人： Shenqing Fang , Tung-Sheng Chen
发明人： Shenqing Fang , Tung-Sheng Chen
IPC分类号： H01L21/336 , H01L21/3105 , H01L21/321 , H01L29/792 , H01L21/28 , H01L27/115 , H01L29/51
CPC分类号： H01L21/28282 , H01L21/28202 , H01L27/11568 , H01L29/518
摘要： Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.
摘要翻译：本技术的实施例针对场效应晶体管的栅极侧壁工程。这些技术包括形成阻挡电介质区域和其表面的氮化。在阻挡电介质区域的氮化之后，在其上形成栅极区域，并且栅极区域的侧壁被氧化以围绕栅极尖锐拐角并减小栅极拐角处的电场。

39. 发明授权

US08637918B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08637918B2
公开(公告)日：2014-01-28
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

40. 发明授权

US08487373B2 SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same 有权
标题翻译：具有不均匀隧道氧化物的SONOS存储单元及其制造方法
公开(公告)号：US08487373B2
公开(公告)日：2013-07-16
申请号：US12432441
申请日：2009-04-29
申请人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
发明人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
IPC分类号： H01L21/331
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/42352
摘要： Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
摘要翻译：公开了形成存储单元的方法。一种方法包括在半导体衬底中形成源极 - 漏极结构，其中源极 - 漏极结构包括圆顶顶表面和侧壁表面。在源极 - 漏极结构的顶壁和侧壁表面上形成氧化物层。形成在源极 - 漏极结构的顶表面上的氧化物层的部分的厚度大于在源极 - 漏极结构的侧壁表面上形成的氧化物层的部分的厚度。

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