专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08484535B2 Error-floor mitigation of codes using write verification 有权
标题翻译：使用写入验证的错误代码减少代码
公开(公告)号：US08484535B2
公开(公告)日：2013-07-09
申请号：US12994288
申请日：2009-04-21
申请人： Nils Graef , Kiran Gunnam
发明人： Nils Graef , Kiran Gunnam
IPC分类号： G11C29/00
CPC分类号： H03M13/1102 , G06F11/1012 , G11B20/1833 , G11B2020/1823 , G11B2020/185 , G11B2220/2516 , G11B2220/61 , H03M13/1108 , H03M13/1142 , H03M13/455
摘要： Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.
摘要翻译：当通道输入（例如，LDPC）码字被写入存储介质时执行，写入验证方法（i）将信道输入码字与写入的码字进行比较，（ii）识别任何错误比特，以及（iii）表中记录的错误位索引。在稍后的时间，写入的码字被读取并发送到解码器。如果解码器出现接近码字失败，则写入错误恢复过程将搜索表并检索错误位信息。调整这些索引处的码字比特，并且修改的码字被提交进一步处理。

32. 发明申请

US20130124590A1 RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT 有权
标题翻译：可重新安装的循环安装
公开(公告)号：US20130124590A1
公开(公告)日：2013-05-16
申请号：US13294332
申请日：2011-11-11
申请人： Kiran Gunnam , Madhusudan Kalluri
发明人： Kiran Gunnam , Madhusudan Kalluri
IPC分类号： G06F7/00
CPC分类号： G06F5/017
摘要： In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement.
摘要翻译：在一个实施例中，可重构循环移位器装置具有串联连接的第一和第二可重构循环移位器，每个可选择性循环移位器可选择性地和独立地配置为一次以三种不同模式中的任何一种运行。在第一模式中，可重构循环移位器被配置为四个4×4循环移位器循环移位四组四个输入值。在第二模式中，可重构循环移位器被配置为两个8×8循环移位器以循环移位两组八个输入值。在第三模式中，可重构循环移位器被配置为一个16×16循环移位器，以循环移位一组16个输入值。因为第一和第二可重构循环移位器是可独立配置的，所以可重构循环移位器装置有九种不同的配置。

33. 发明授权

US08316272B2 Error-correction decoder employing multiple check-node algorithms 有权
标题翻译：纠错解码器采用多个校验节点算法
公开(公告)号：US08316272B2
公开(公告)日：2012-11-20
申请号：US12680810
申请日：2009-04-08
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors.
摘要翻译：在一个实施例中，LDPC解码器具有控制器和一个或多个校验节点单元（CNU）。 CNU使用缩放的最小和算法，偏移最小和算法或缩放和偏移最小和算法来生成校验节点消息。最初，控制器选择缩放因子和偏移值。缩放因子可以被设置为一，不进行缩放，并且偏移值可以被设置为零而不进行偏移。如果解码器不能正确解码码字，则（i）控制器选择新的缩放和/或偏移值，并且（ii）解码器尝试使用新的缩放和/或偏移值来正确解码码字。通过改变缩放因子和/或偏移值，本发明的LDPC解码器可能能够改善仅使用固定或不缩放因子或固定或不具有偏移因子的LDPC解码器的误码本底特性。

34. 发明授权

US08196010B1 Generic encoder for low-density parity-check (LDPC) codes 有权
标题翻译：用于低密度奇偶校验（LDPC）码的通用编码器
公开(公告)号：US08196010B1
公开(公告)日：2012-06-05
申请号：US12187858
申请日：2008-08-07
申请人： Kiran Gunnam , Nedeljko Varnica
发明人： Kiran Gunnam , Nedeljko Varnica
IPC分类号： G06F11/00
CPC分类号： H03M13/1102 , G06F11/1032 , H03M13/1148 , H03M13/116 , H03M13/118 , H03M13/1188 , H03M13/3776 , H03M13/458 , H03M13/616 , H03M13/6527 , H03M13/6544
摘要： Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.
摘要翻译：提供了用于使用各种反转机制基于LDPC码对数据进行编码以获得奇偶位的系统和方法。在一些实施例中，LDPC编码器可以使用推测递归和校正机制来计算奇偶校验位。在这些实施例中，LDPC编码器可以使用至少一个推测值来代替奇偶校验分量的实际值来发起递归。然后可以使用校正因子校正推测值。在其他实施例中，提供了可以执行块反转机制的LDPC编码器。该机制可以用于具有奇偶校验部分的奇偶校验矩阵的LDPC码，部分由大三角矩阵组成。在其他实施例中，提供通用LDPC编码器。通用LDPC编码器可以实现各种不同的编码技术，例如不同的反转机制，并且可以是基于处理器的或基于有限状态机的。

35. 发明申请

US20120079340A1 COMMUNICATIONS SYSTEM EMPLOYING LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING 失效
标题翻译：通信系统采用本地和全球交互/去交互
公开(公告)号：US20120079340A1
公开(公告)日：2012-03-29
申请号：US12891161
申请日：2010-09-27
申请人： Kiran Gunnam , Yang Han
发明人： Kiran Gunnam , Yang Han
IPC分类号： H03M13/11 , H04L27/06 , G06F11/10 , H04L27/00
CPC分类号： H04L25/03171 , H03M13/09 , H03M13/1137 , H03M13/116 , H03M13/2732 , H03M13/2792 , H03M13/2796 , H03M13/41 , H03M13/6331 , H03M13/6561 , H03M13/6566 , H04L1/0045 , H04L1/0057 , H04L1/0071
摘要： In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path.
摘要翻译：在一个实施例中，通信系统具有写入路径和读取路径。在写入路径中，本地/全局交织器交织用户数据流，并且纠错（EC）编码器对用户数据流进行编码以生成EC码字。本地/全局解交织器对EC码字的奇偶校验位进行解交织，并且经由噪声信道发送原始未交织的用户数据和去交织的奇偶校验位。在读取路径中，信道检测器恢复对应于码字的信道软输出值。本地/全局交织器对信道值进行交织，并且EC解码器解码交织值以恢复在写入路径中生成的原始码字。解复用器从奇偶校验位解复用用户数据。然后，本地/全局解交织器对用户数据进行解交织以获得最初在写入路径处接收的用户数据的原始序列。

36. 发明申请

US20120017132A1 LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING 有权
标题翻译：本地和全球交互/去交互
公开(公告)号：US20120017132A1
公开(公告)日：2012-01-19
申请号：US12835989
申请日：2010-07-14
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0071 , H03M13/09 , H03M13/1137 , H03M13/116 , H03M13/2778 , H03M13/2957 , H03M13/41 , H03M13/6331 , H04L1/0045 , H04L1/0057
摘要： In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing.
摘要翻译：在一个实施例中，解交织器接收对应于LDPC编码码字的比特的软输出值。解交织器具有临时存储器，其向本地解交织器提供软输出值的集合。每组中的值的数量等于LDPC H矩阵的块列中的列数。每个集合具有对应于LDPC H矩阵的至少两个不同块列的至少两个软输出值子集，其中至少两个子集的各个软输出值彼此交错。对每个集合执行本地解交织，使得每个子集的软输出值被分组在一起。然后对子集执行全局解交织，使得对应于H矩阵的相同块列的子集被布置在一起。在另一个实施例中，交织器执行全局然后本地交织以执行去交织器处理的逆。

37. 发明申请

US20120005551A1 BREAKING TRAPPING SETS USING TARGETED BIT ADJUSTMENT 有权
标题翻译：使用目标位调整打破抓包
公开(公告)号：US20120005551A1
公开(公告)日：2012-01-05
申请号：US12827652
申请日：2010-06-30
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/3707 , H03M13/09 , H03M13/1108 , H03M13/1111 , H03M13/1128 , H03M13/1142 , H03M13/3723 , H03M13/373 , H03M13/451 , H03M13/6306 , H03M13/6591
摘要： In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial.
摘要翻译：在一个实施例中，LDPC解码器执行目标比特调整方法以在解码器失败之后恢复有效码字。在第一阶段中，后处理器通过将解码器在最后（即失败）迭代期间输出的LLR值饱和为相对较小的值来初始化解码器。然后，进行两比特试验，其中在每个试验中调整对应于码字的两个比特的LLR值。以调整后的值进行解码，如果不满足的校验节点的数量超过规定的阈值，则进行第二阶段。后处理器通过在第一级的最后（即失败的）迭代中将解码器输出的LLR值饱和到相对较小的值来初始化解码器。第二级然后执行单位调整试验，其中在每个试验中调整对应于码字的一个比特的一个LLR值。

38. 发明申请

US20110138253A1 RAM LIST-DECODING OF NEAR CODEWORDS 有权
标题翻译： RAM列表 - 近似编码的解码
公开(公告)号：US20110138253A1
公开(公告)日：2011-06-09
申请号：US12675981
申请日：2008-12-12
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： Certain embodiments of the present invention are efficient run-time methods for creating and updating a RAM list of dominant trapping-set profiles for use in (LDPC) list decoding. A decoded correct codeword is compared to a near codeword to generate a new trapping-set profile, and the profile written to RAM. Record is kept of how many times RAM has been searched since a profile was last matched. Profiles that have not been matched within a specified number of searches are purge-eligible. Purge-eligible profiles are further ranked on other factors, e.g., number of times a profile has been matched since it was added, number of unsatisfied check nodes, number of erroneous bit nodes. If there is insufficient free space in RAM to store a newly-discovered profile, then purge-eligible profiles are deleted, beginning with the lowest-ranked profiles, until either (i) sufficient free space is created or (ii) there are no more purge-eligible profiles.
摘要翻译：本发明的某些实施例是用于创建和更新用于（LDPC）列表解码的主要陷阱集简档的RAM列表的有效的运行时方法。将解码的正确码字与近似码字进行比较，以产生新的陷阱集简档，并将该轮廓写入RAM。自上次匹配个人资料以来，记录被保留了多少次RAM的搜索。在指定数量的搜索中未匹配的配置文件符合资格。清除符合条件的配置文件被进一步排列在其他因素上，例如，自添加配置文件以来匹配的次数，不满足的校验节点数量，错误位节点数量。如果RAM中没有足够的可用空间来存储新发现的配置文件，则从排名最低的配置文件开始，删除符合条件的配置文件，直到（i）创建足够的可用空间或（ii）没有更多空间清除符合条件的配置文件。

39. 发明申请

US20100042903A1 RECONFIGURABLE ADDER 有权
标题翻译：可重新添加
公开(公告)号：US20100042903A1
公开(公告)日：2010-02-18
申请号：US12492328
申请日：2009-06-26
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/45 , G06F7/50 , H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums.
摘要翻译：在一个实施例中，可重配置加法器具有第一和第二五位不可重新配置的加法器，并且可选择性地配置为以五位模式或十位模式操作。在五位模式中，第一不可重新配置的加法器将第一和第二消息相加以产生第一和，并且第二不可重配置加法器添加第三和第四消息以产生第二和。在十位模式中，第一不可重配置加法器将第一十位消息的前半部分和第二十位消息的前半部分相加，以产生第一部分和和结转位。第二不可重新配置的加法器将第一十位消息的后半部分，第二十位消息的后半部分和进位位相加，以产生第二部分和。然后通过组合第一和第二部分和来生成十位和。

40. 发明申请

US20100042894A1 ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING LMAXB-BASED SELECTION OF ALTERNATIVE LAYERED-DECODING SCHEDULES 有权
标题翻译：使用基于LMAXB的选择替代层级解码方案的层级解码器的错误地面缓解
公开(公告)号：US20100042894A1
公开(公告)日：2010-02-18
申请号：US12510639
申请日：2009-07-28
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： A decoder-implemented method for layered decoding that, when the decoder converges on a near codeword using an initial schedule, (i) selects a subsequent schedule from a schedule set based on the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes and (ii) re-performs decoding using the subsequent schedule. When used in an offline schedule-testing system, the layered-decoding method (i) identifies which schedules, out of a population of schedules, correctly decode a decoder input codeword and (ii) associates the identified schedules with the Lmaxb value of the near codeword.
摘要翻译：一种用于分层解码的解码器实现方法，当解码器使用初始调度收敛在近似码字上时，（i）从基于近码字的层Lmaxb的调度集中选择后续调度，哪个层包含最大数目的不满足的校验节点和（ii）使用随后的调度重新执行解码。当在离线时间表测试系统中使用时，分层解码方法（i）识别从时间表中的哪些日程表正确解码解码器输入码字，并且（ii）将所识别的时间表与近邻的时间表的Lmaxb值相关联码字。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式