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31. 发明授权

US5907313A Matrix-type display device 失效
标题翻译：矩阵式显示装置
公开(公告)号：US5907313A
公开(公告)日：1999-05-25
申请号：US743990
申请日：1996-11-05
申请人： Yasushi Kubota , Kenichi Katoh , Hidehiko Chimura , Jun Koyama
发明人： Yasushi Kubota , Kenichi Katoh , Hidehiko Chimura , Jun Koyama
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1368 , G09G3/36 , G11C19/00 , H01L29/786
CPC分类号： G09G3/3677 , G09G2330/021 , G09G2330/022
摘要： A matrix-type display device in which a number of pixels are arranged and a scanning line and a signal line to which a display signal is output are connected to each pixel. A signal line driver circuit in which a decoder circuit is controlled by a counter circuit, or a scanning line driver circuit in which a decoder circuit is controlled by a counter circuit is divided into a plurality of sections. A clock signal and/or a power supply voltage is selectively supplied to the respective sections.
摘要翻译：其中排列有多个像素并且将扫描线和输出显示信号的信号线连接到每个像素的矩阵型显示装置。其中解码器电路由计数器电路控制的信号线驱动器电路或其中解码器电路由计数器电路控制的扫描线驱动器电路被分成多个部分。选择性地将时钟信号和/或电源电压提供给各个部分。

32. 发明授权

US06879313B1 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
标题翻译：移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法
公开(公告)号：US06879313B1
公开(公告)日：2005-04-12
申请号：US09523511
申请日：2000-03-10
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36 , G11C19/28 , G11C19/00
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
摘要翻译：移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路线和多个锁存电路。在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

33. 发明授权

US5926234A Liquid crystal display device 失效
标题翻译：液晶显示装置
公开(公告)号：US5926234A
公开(公告)日：1999-07-20
申请号：US877567
申请日：1997-06-17
申请人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
发明人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1362 , G02F1/1368 , G09G3/36 , H01L29/78 , H01L29/786 , G02F1/1333 , G02F1/1345 , H01L23/62
CPC分类号： G02F1/13454 , G02F1/136204 , G02F2001/136254 , G09G3/3611 , H01L2924/0002
摘要： Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
摘要翻译：用于驱动各个像素的图像元件和驱动电路单片地形成在绝缘基板上。提供保护电路，用于当产生不小于预定值的电位差时允许驱动电路的输入输出端子导通。保护电路包括MOS晶体管，并且其导通电压根据栅绝缘层的厚度设定。当形成驱动电路时，保护电路同时形成在绝缘基板上。在这种布置中，由于根据栅极绝缘层的厚度设定导通电压并且可以容易地调节厚度，所以可以实现准确的导通电压。由于该装置防止制造成本的增加，因此可以可靠地保护驱动电路等，以免在制造过程中产生的静电和正常操作中的输入浪涌。

34. 发明申请

US20050168252A1 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 失效
公开(公告)号：US20050168252A1
公开(公告)日：2005-08-04
申请号：US11063718
申请日：2005-02-23
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36 , G11C19/28 , H03L7/00
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

35. 发明授权

US5898322A Logic circuit for liquid crystal display having pass-transistor logic circuitry and thin film transistors 失效
标题翻译：具有传输晶体管逻辑电路和薄膜晶体管的液晶显示器的逻辑电路
公开(公告)号：US5898322A
公开(公告)日：1999-04-27
申请号：US524503
申请日：1995-09-07
申请人： Yasushi Kubota , Hiroshi Yoneda
发明人： Yasushi Kubota , Hiroshi Yoneda
IPC分类号： G02F1/133 , G11C19/00 , H01L27/12 , H03K19/0175 , H03K19/173 , H03K19/21 , H03K19/094 , H01L27/00
CPC分类号： H03K19/215 , H03K19/1737
摘要： A logic circuit performs a logic operation on a plurality of input logic signals and outputting a resultant logic signal. The logic circuit comprises a pass-transistor logic circuit including: a plurality of field effect transistors, at least two of the plurality of field effect transistors being coupled in series, a gate electrode of each of the at least two field effect transistors receiving a corresponding first logic signal, and one of drain and source electrodes ditto receiving a corresponding second logic signal; and a node for coupling the other of the drain and source electrodes of the at least two field effect transistors, and for outputting the resultant logic signal. The plurality of field effect transistors are thin film transistors (TFTs).
摘要翻译：逻辑电路对多个输入逻辑信号执行逻辑运算并输出合成的逻辑信号。逻辑电路包括一个通过晶体管逻辑电路，包括：多个场效应晶体管，多个场效应晶体管中的至少两个串联耦合，所述至少两个场效应晶体管中的每一个的栅电极接收相应的第一逻辑信号，以及漏极和源极之一，同时接收对应的第二逻辑信号; 以及用于耦合所述至少两个场效应晶体管的所述漏极和源极中的另一个的节点，并用于输出所得到的逻辑信号。多个场效应晶体管是薄膜晶体管（TFT）。

36. 发明授权

US5671026A Liquid crystal display device with TFT ESD protective devices between I/O terminals or with a short circuited alignment film 失效
标题翻译：具有I / O端子之间的TFT ESD保护装置或短路对准膜的液晶显示装置
公开(公告)号：US5671026A
公开(公告)日：1997-09-23
申请号：US394626
申请日：1995-02-27
申请人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
发明人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1362 , G02F1/1368 , G09G3/36 , H01L29/78 , H01L29/786 , G02F1/1333 , G02F1/1337 , H01L23/62
CPC分类号： G02F1/13454 , G02F1/136204 , G02F2001/136254 , G09G3/3611 , H01L2924/0002
摘要： Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
摘要翻译：用于驱动各个像素的图像元件和驱动电路单片地形成在绝缘基板上。提供保护电路，用于当产生不小于预定值的电位差时允许驱动电路的输入输出端子导通。保护电路包括MOS晶体管，并且其导通电压根据栅绝缘层的厚度设定。当形成驱动电路时，保护电路同时形成在绝缘基板上。在这种布置中，由于根据栅极绝缘层的厚度设定导通电压并且可以容易地调节厚度，所以可以实现准确的导通电压。由于该装置防止制造成本的增加，因此可以可靠地保护驱动电路等，以免在制造过程中产生的静电和正常操作中的输入浪涌。

37. 发明授权

US07173598B2 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
公开(公告)号：US07173598B2
公开(公告)日：2007-02-06
申请号：US11063718
申请日：2005-02-22
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

38. 发明授权

US6067066A Voltage output circuit and image display device 失效
标题翻译：电压输出电路和图像显示装置
公开(公告)号：US6067066A
公开(公告)日：2000-05-23
申请号：US712644
申请日：1996-09-11
申请人： Yasushi Kubota , Osamu Sasaki , Hiroshi Yoneda
发明人： Yasushi Kubota , Osamu Sasaki , Hiroshi Yoneda
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G3/3655 , G09G2310/0259 , G09G2310/027 , G09G2310/0297
摘要： A voltage output circuit has decoders, a selecting circuit, a logical circuit and an output circuit in order to select one of plural gradation power source lines for a prescribed period based upon k bits and m bits of an n-bit digital signal. The k bits of the digital signal are converting into 2.sup.k decoded signals by one decoder, and another m bits are converted into 2.sup.m decoded signals by the other decoder. The selecting circuit generates a signal for selecting one of periods which were obtained by dividing one horizontal scanning period into 2.sup.k based upon k-numbered timing signals by using the 2.sup.k decoded signals. The logical circuit generates 2.sup.n signals composed of combinations of the signals from the selecting circuit and the 2.sup.m decoded signals. Moreover, one of the 2.sup.m gradation power source lines is selected by an output switch by using the signal from the logical circuit. As a result, in an image display device using a digital signal as an input video signal, a number of gradation power source lines is reduced and the arrangement of driving circuits is simplified without deteriorating display quality. As a result, a cost of the image display device can be lowered.
摘要翻译：电压输出电路具有解码器，选择电路，逻辑电路和输出电路，以便基于n比特数字信号的k比特和m比特来选择多个灰度级电源线中的一个规定时段。数字信号的k位由一个解码器转换成2k个解码信号，另一个m位由另一个解码器转换成2m个解码信号。选择电路通过使用2k个解码信号，生成用于选择通过基于k个编号的定时信号将一个水平扫描周期分成2k而获得的周期之一的信号。逻辑电路产生由来自选择电路的信号和2m个解码信号的组合组成的2n个信号。此外，通过使用来自逻辑电路的信号，由输出开关选择2m级的电源线之一。结果，在使用数字信号作为输入视频信号的图像显示装置中，减少了多个灰度电源线，并且简化了驱动电路的布置，而不会降低显示质量。结果，可以降低图像显示装置的成本。

39. 发明授权

US5844538A Active matrix-type image display apparatus controlling writing of display data with respect to picture elements 失效
标题翻译：有源矩阵型图像显示装置控制对图像元素的显示数据的写入
公开(公告)号：US5844538A
公开(公告)日：1998-12-01
申请号：US363218
申请日：1994-12-23
申请人： Ichiro Shiraki , Manabu Matsuura , Yasushi Kubota , Hiroshi Yoneda , Yoshitaka Yamamoto
发明人： Ichiro Shiraki , Manabu Matsuura , Yasushi Kubota , Hiroshi Yoneda , Yoshitaka Yamamoto
IPC分类号： G09G3/36 , G09G5/399
CPC分类号： G09G3/3648 , G09G2300/0814 , G09G2300/0842 , G09G2310/0235 , G09G2320/0219 , G09G2320/0247 , G09G3/3659 , G09G3/3666 , G09G5/399
摘要： An image display apparatus can be arranged so that a picture element capacity obtains a value provides display data retention of less than 99% by writing same data to a picture element a plurality of times during 1 frame period. This makes it possible to disuse the auxiliary capacity and to improve an aperture ratio. Moreover, with the present invention, an MOS transistor arranged in each picture element as a switching element for driving the picture element, a scan signal line driving circuit and a data signal line driving circuit for transmitting a driving signal based upon display data to the MOS transistor through a data signal line and a scan signal line, and a first frame memory and a second frame memory provided outside the picture element for storing display data to be outputted to a data signal line driving circuit for 1 frame are formed on one substrate. As a result, it is possible to improve package efficiency and lower cost by using a driver monolithic technique.
摘要翻译：图像显示装置可以被布置为使得通过在1帧周期期间将相同的数据多次写入到图像元素中，图像元素容量获得提供小于99％的显示数据保持。这使得可以消除辅助容量并提高开口率。此外，根据本发明，配置在每个像素中的MOS晶体管作为用于驱动像素的开关元件，扫描信号线驱动电路和数据信号线驱动电路，用于根据显示数据向MOS发送驱动信号晶体管通过数据信号线和扫描信号线，并且在一个基板上形成用于存储要输出到1帧的数据信号线驱动电路的显示数据的图像元件外部的第一帧存储器和第二帧存储器。结果，可以通过使用驱动器单片技术来提高封装效率和降低成本。

40. 发明授权

US08325170B2 Image display device and driving method thereof 失效
标题翻译：图像显示装置及其驱动方法
公开(公告)号：US08325170B2
公开(公告)日：2012-12-04
申请号：US12639049
申请日：2009-12-16
申请人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
发明人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0297
摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.
摘要翻译：图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。信号线驱动电路中的存储电路和D / A转换电路通常用于n（n为等于或大于2的自然数）信号线。一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。因此，可以驱动所有的信号线。因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

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