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31. 发明申请

US20060022732A1 DPWM with leading edge blanker circuit 有权
标题翻译： DPWM具有前沿消隐电路
公开(公告)号：US20060022732A1
公开(公告)日：2006-02-02
申请号：US11096187
申请日：2005-03-31
申请人： Kafai Leung , Ka Leung , Jinwen Xiao
发明人： Kafai Leung , Ka Leung , Jinwen Xiao
IPC分类号： H03K3/017
CPC分类号： H03M1/0863 , G06F1/025 , H03M1/822
摘要： An apparatus for providing over current protection for a digital pulse width modulator is disclosed. The apparatus includes first logic circuitry for generating a primary interrupt indicating that a detected output current is greater than a threshold current. Second logic circuitry blanks out current spikes in the output current occurring on a leading pulse edge of at least one of a plurality of outputs of the digital pulse-width modulator.
摘要翻译：公开了一种用于为数字脉宽调制器提供过流保护的装置。该装置包括用于产生指示检测到的输出电流大于阈值电流的主中断的第一逻辑电路。第二逻辑电路消除在数字脉冲宽度调制器的多个输出中的至少一个的前导脉冲沿出现的输出电流中的电流尖峰。

32. 发明申请

US20050280458A1 Low power PLL for PWM switching digital control power supply 有权
标题翻译：低功耗PLL用于PWM开关数字控制电源
公开(公告)号：US20050280458A1
公开(公告)日：2005-12-22
申请号：US10872702
申请日：2004-06-21
申请人： Ka Leung , Kafai Leung
发明人： Ka Leung , Kafai Leung
IPC分类号： H02M3/335 , H03K3/017 , H03K5/00 , H03K5/13 , H03K7/08 , H03L7/099
CPC分类号： H02M3/33576 , H03K5/133 , H03K7/08 , H03K2005/00032 , H03K2005/00156 , H03K2005/00202 , H03L7/0805 , H03L7/0996
摘要： A timing source for a pulse generator is disclosed, which timing source includes an input for receiving a reference clock output at a reference operating frequency. An edge generator is provided for generating a plurality of clock edges from an edge of the reference clock during one period thereof, with the spacing of the plurality of clock edges being a multiple of a predetermined divisor. As such, the resolution of such spacing emulates a higher clock frequency than the reference operating frequency. A selector then selects one of the plurality of clock edges from a reference one thereof to define the width of a pulse.
摘要翻译：公开了用于脉冲发生器的定时源，该定时源包括用于以参考工作频率接收参考时钟输出的输入。边缘发生器被提供用于在其一个周期期间从参考时钟的边缘产生多个时钟边缘，多个时钟边沿的间隔是预定除数的倍数。因此，这种间隔的分辨率模拟比参考工作频率更高的时钟频率。然后，选择器从其参考一个中选择多个时钟边沿中的一个来定义脉冲的宽度。

33. 发明申请

US20050219108A1 METHOD AND APPARATUS FOR SUBCLOCKING A SAR ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：用于封装SAR模拟到数字转换器的方法和装置
公开(公告)号：US20050219108A1
公开(公告)日：2005-10-06
申请号：US10816564
申请日：2004-03-31
申请人： Douglas Piasecki , Ka Leung , Kenneth Fernald
发明人： Douglas Piasecki , Ka Leung , Kenneth Fernald
IPC分类号： H03M1/12 , H03M1/34 , H03M1/46 , H03M1/50
CPC分类号： H03M1/124 , H03M1/462
摘要： Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracked during a tracking phase to sample the value thereof. A conversion cycle referenced to an edge of the low frequency clock is then initiated. The sampled data is then converted in a conversion operation during a data conversion cycle, which conversion operation requires a plurality of conversion clock cycles. The timing of at least a portion of the conversion operation is controlled during the data conversion cycle utilizing the high frequency clock as the conversion clock.
摘要翻译： SAR模数转换器的次频方法和装置。公开了一种用于计时SAR模数转换器（ADC）的操作的方法。提供了低频时钟和高频时钟。然后在跟踪阶段跟踪模拟输入电压以对其值进行采样。然后启动参考低频时钟边沿的转换周期。然后在数据转换周期期间，在转换操作中转换采样数据，该转换操作需要多个转换时钟周期。在利用高频时钟作为转换时钟的数据转换周期期间，控制转换操作的至少一部分的定时。

34. 发明申请

US20050219065A1 Gain control for delta sigma analog-to-digital converter 有权
标题翻译：增量控制用于Δ-Σ模数转换器
公开(公告)号：US20050219065A1
公开(公告)日：2005-10-06
申请号：US10816266
申请日：2004-03-31
申请人： Douglas Holberg , Ka Leung
发明人： Douglas Holberg , Ka Leung
IPC分类号： H03M1/22 , H03M3/02
CPC分类号： H03M3/484 , H03M3/49
摘要： Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an integration capacitor connected between the non-inverting input and the output. An input voltage is sampled at a first rate onto an input sampling capacitor and then charge is dumped from the input sampling capacitor to the non-inverting input of the amplifier at a second time and at the first rate. A reference voltage is sampled onto a feedback sampling capacitor at substantially the first rate, and charge stored on the feedback sampling capacitor is dumped to the non-inverting input of the amplifier at a second rate different than the first rate. The amount of time that charge is dumped from the feedback sampling capacitor is controlled to be substantially equal to the amount of time that charge is being dumped from the input sampling capacitor, wherein varying the second rate relative to the first rate changes the gain of delta-sigma converter
摘要翻译：增量控制用于Δ-Σ模数转换器。公开了一种用于驱动积分器的输入的方法，该Δ-Σ转换器具有放大器，其具有连接到参考电压的非反相输入，输出和正输入以及连接在非反相输入和输出。输入电压以第一速率被采样到输入采样电容器上，然后在第二时间和第一速率将电荷从输入采样电容器转储到放大器的非反相输入端。以基本上第一速率将参考电压采样到反馈采样电容器上，并且存储在反馈采样电容器上的电荷以不同于第一速率的第二速率被转储到放大器的非反相输入端。从反馈采样电容器转储电荷的时间量被控制为基本上等于从输入采样电容器转储电荷的时间量，其中相对于第一速率改变第二速率改变增量 -Σ转换器

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