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31. 发明授权

US07129174B2 Methods of fabricating a semiconductor substrate for reducing wafer warpage 失效
公开(公告)号：US07129174B2
公开(公告)日：2006-10-31
申请号：US10806521
申请日：2004-03-23
申请人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
发明人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0209 , H01L21/302 , H01L21/6708 , H01L21/76895 , H01L27/10844 , H01L27/10882 , H01L29/7842
摘要： Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.

32. 发明授权

US07118975B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07118975B2
公开(公告)日：2006-10-10
申请号：US10872360
申请日：2004-06-22
申请人： Jae-Jong Han , Young-Wook Park , Jae-Hyun Yeo
发明人： Jae-Jong Han , Young-Wook Park , Jae-Hyun Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/76235 , H01L21/823481 , H01L27/105 , H01L27/1052 , H01L27/10876
摘要： Provided is a method for manufacturing semiconductor devices including channel trenches that are separated by isolation structures. According to the process, the substrate is etched to form isolation trenches after which a sidewall oxide layer, a liner nitride layer and a field oxide layer are subsequently formed on the substrate and in the isolation trenches. The substrate is then planarized to remove upper portions of the sidewall oxide layer, the liner nitride layer and the field oxide layer to expose surface portions of the substrate between adjacent isolation trench structures. Channel trenches are then formed in the exposed surface portions of the substrate leaving residual substrate regions adjacent the isolation trench structures. These residual substrate regions are then oxidized and removed to form improved second channel trenches for the formation of transistor regions.
摘要翻译：提供一种半导体器件的制造方法，其包括由隔离结构分离的沟槽。根据该过程，蚀刻衬底以形成隔离沟槽，之后随后在衬底和隔离沟槽中形成侧壁氧化物层，衬里氮化物层和场氧化物层。然后将衬底平坦化以除去侧壁氧化物层，衬里氮化物层和场氧化物层的上部，以暴露在相邻的隔离沟槽结构之间的衬底的表面部分。然后在衬底的暴露的表面部分中形成通道沟槽，留下邻近隔离沟槽结构的残余衬底区域。然后将这些残留的衬底区域氧化并除去以形成用于形成晶体管区域的改进的第二沟道沟槽。

33. 发明申请

US20050233559A1 Method of forming a layer on a wafer 失效
标题翻译：在晶片上形成层的方法
公开(公告)号：US20050233559A1
公开(公告)日：2005-10-20
申请号：US11061407
申请日：2005-02-18
申请人： Ji-Sang Yahng , Young-Wook Park , Jae-Jong Han , Jum-Soo Chang
发明人： Ji-Sang Yahng , Young-Wook Park , Jae-Jong Han , Jum-Soo Chang
IPC分类号： H01L21/31 , H01L21/00 , H01L21/20 , H01L21/205 , H01L21/316
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/67109 , H01L21/67757 , Y10S414/136 , Y10S414/139
摘要： A layer is formed on a semiconductor wafer in an apparatus having a processing chamber, a transferring chamber, and a wafer boat. The boat having the semiconductor wafer thereon is rotated in the transferring chamber. While the boat is rotated, the boat is transferred between the transferring chamber and the processing chamber and a reaction gas is provided to the processing chamber to form the layer on the wafer.
摘要翻译：在具有处理室，转印室和晶片舟皿的装置中的半导体晶片上形成层。其上具有半导体晶片的船在转印室中旋转。当船旋转时，船在转移室和处理室之间转移，并且反应气体被提供到处理室以在晶片上形成层。

34. 发明申请

US20050140110A1 Multi-link rear suspension system 有权
标题翻译：多连杆后悬挂系统
公开(公告)号：US20050140110A1
公开(公告)日：2005-06-30
申请号：US11005405
申请日：2004-12-06
申请人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
发明人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
IPC分类号： B60G3/20 , B60G3/06 , B60G3/12 , B60G7/00 , B60G7/02 , B60G13/06 , B60G15/06 , B62D21/00 , F16F3/10 , F16F15/04 , F16F15/08
CPC分类号： B60G3/202 , B60G7/001 , B60G7/008 , B60G2200/1442 , B60G2200/184 , B60G2202/12 , B60G2202/24 , B60G2204/1244 , B60G2204/143 , B60G2204/148 , B60G2204/15 , B60G2206/50
摘要： A knuckle is minimized in size to be located in an internal space of a rear wheel. An upper arm is disposed lower than a conventional double wishbone type and one end of the upper arm is secured to the knuckle. A shock absorber couples at a lower end thereof to the knuckle by passing through a space between a lower arm and assist arm. This configuration thus constructed greatly increases the space of the trunk room, reduces noise by minimizing the transmission of road impact and vibration, and improves ride comfort as well as braking stability and turn stability.
摘要翻译：转向节的尺寸被最小化以位于后轮的内部空间中。上臂布置成低于传统的双叉骨型，并且上臂的一端固定在转向节上。减震器通过穿过下臂和辅助臂之间的空间在其下端处连接到转向节。这样构造大大增加了行李箱的空间，通过最小化道路冲击和振动的传递来降低噪音，并且提高乘坐舒适度以及制动稳定性和转向稳定性。

35. 发明申请

US20080029031A1 METHODS AND APPARATUS FOR FORMING THIN FILMS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于形成半导体器件薄膜的方法和装置
公开(公告)号：US20080029031A1
公开(公告)日：2008-02-07
申请号：US11838998
申请日：2007-08-15
申请人： Jae-Hyun Yeo , Young-Wook Park , Ki-Chul Kim , Jae-Jong Han
发明人： Jae-Hyun Yeo , Young-Wook Park , Ki-Chul Kim , Jae-Jong Han
IPC分类号： C23C16/54
CPC分类号： C23C16/44 , H01L21/28562 , H01L21/3141 , H01L21/31604 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691
摘要： Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically absorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically absorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically absorb the second reactant onto the substrate.
摘要翻译：提供了用于形成用于半导体器件的薄膜的方法和装置，其能够通过在预定温度下预热和提供处理气体和净化气体来形成薄膜来提供和除去含有待形成的薄膜的构成元素的反应物在基板上。例如，形成薄膜的方法包括将第一反应物供应到室以将第一反应物化学吸收到基底上，第一反应物被预热的第一气体鼓泡，清洗室以除去基底上的残留物使所述第一反应物被化学吸收，并且通过向所述室供应第二反应物以化学吸收所述第二反应物到所述衬底上，通过化学位移形成所述薄膜。

36. 发明授权

US07243934B2 Multi-link rear suspension system 有权
标题翻译：多连杆后悬挂系统
公开(公告)号：US07243934B2
公开(公告)日：2007-07-17
申请号：US11005405
申请日：2004-12-06
申请人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
发明人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
IPC分类号： B60G3/12
CPC分类号： B60G3/202 , B60G7/001 , B60G7/008 , B60G2200/1442 , B60G2200/184 , B60G2202/12 , B60G2202/24 , B60G2204/1244 , B60G2204/143 , B60G2204/148 , B60G2204/15 , B60G2206/50
摘要： A knuckle is minimized in size to be located in an internal space of a rear wheel. An upper arm is disposed lower than a conventional double wishbone type and one end of the upper arm is secured to the knuckle. A shock absorber couples at a lower end thereof to the knuckle by passing through a space between a lower arm and assist arm. This configuration thus constructed greatly increases the space of the trunk room, reduces noise by minimizing the transmission of road impact and vibration, and improves ride comfort as well as braking stability and turn stability.
摘要翻译：转向节的尺寸被最小化以位于后轮的内部空间中。上臂布置成低于传统的双叉骨型，并且上臂的一端固定在转向节上。减震器通过穿过下臂和辅助臂之间的空间在其下端处连接到转向节。这样构造大大增加了行李箱的空间，通过最小化道路冲击和振动的传递来降低噪音，并且提高乘坐舒适度以及制动稳定性和转向稳定性。

37. 发明申请

US20060115954A1 Methods of manufacturing a capacitor and a semiconductor device 审中-公开
标题翻译：制造电容器和半导体器件的方法
公开(公告)号：US20060115954A1
公开(公告)日：2006-06-01
申请号：US11265937
申请日：2005-11-03
申请人： Woo-Seok Shim , Young-Wook Park , Jung-Hyeon Lee , Kwang-Sub Yoon , Chul-Ho Kim , Tae-Jin Park
发明人： Woo-Seok Shim , Young-Wook Park , Jung-Hyeon Lee , Kwang-Sub Yoon , Chul-Ho Kim , Tae-Jin Park
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： In methods of manufacturing a capacitor and a semiconductor device, a mold layer is formed on a substrate having a contact plug. The mold layer includes an opening exposing the contact plug. A conductive layer is formed on the contact plug, an inner sidewall of the opening and the mold layer. A photoresist pattern is formed to substantially fill the opening. A cylindrical lower electrode is formed by partially removing the conductive layer. The mold layer is selectively removed while the photoresist pattern prevents damage to the lower electrode, the contact plug and the substrate. The photoresist pattern is removed, and then a dielectric layer and an upper electrode are sequentially formed on the lower electrode. Damage to the lower electrode and the contact plug are effectively prevented due to the presence of the photoresist pattern during selective removal of the mold layer.
摘要翻译：在制造电容器和半导体器件的方法中，在具有接触插塞的基板上形成模层。模具层包括露出接触塞的开口。在接触插塞，开口的内侧壁和模具层上形成导电层。形成光致抗蚀剂图案以基本上填充开口。通过部分去除导电层形成圆柱形下电极。选择性地去除模具层，同时光刻胶图案防止损坏下部电极，接触插塞和基板。去除光致抗蚀剂图案，然后在下电极上依次形成电介质层和上电极。由于在选择性去除模具层期间存在光致抗蚀剂图案，因此有效地防止了下电极和接触插塞的损坏。

38. 发明申请

US20060073670A1 Method of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060073670A1
公开(公告)日：2006-04-06
申请号：US11243397
申请日：2005-10-03
申请人： Yong-Kug Bae , Kwang-Sub Yoon , Young-Wook Park , Jung-Hyeon Lee
发明人： Yong-Kug Bae , Kwang-Sub Yoon , Young-Wook Park , Jung-Hyeon Lee
IPC分类号： H01L21/20 , H01L21/4763 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/7682 , H01L27/10852 , H01L27/10894
摘要： In one embodiment, first and second multi-layer pattern structures are formed over first and second regions of a substrate, respectively. The first and second multi-layer pattern structures include first and second support layer patterns, respectively. The first and second multi-layer pattern structures define first and second openings, respectively. The first and second openings partially expose a portion of the first region and a portion of the second region, respectively. First and second liner patterns are formed on an inner face of the first opening and an inner face of the second opening, respectively. A first etching process is performed on the first multi-layer pattern structure until the first support layer pattern is removed. A second etching process is performed to remove the second multi-layer pattern structure except for the second support layer pattern.
摘要翻译：在一个实施例中，分别在衬底的第一和第二区域上形成第一和第二多层图案结构。第一和第二多层图案结构分别包括第一和第二支撑层图案。第一和第二多层图案结构分别限定第一和第二开口。第一和第二开口分别部分地暴露第一区域的一部分和第二区域的一部分。第一和第二衬里图案分别形成在第一开口的内表面和第二开口的内表面上。对第一多层图案结构进行第一蚀刻处理，直到第一支撑层图案被去除。执行第二蚀刻处理以除去除了第二支撑层图案之外的第二多层图案结构。

39. 发明授权

US06700153B2 One-cylinder stack capacitor and method for fabricating the same 有权
公开(公告)号：US06700153B2
公开(公告)日：2004-03-02
申请号：US10136385
申请日：2002-05-02
申请人： Jung-Hwan Oh , Ki-Hyun Hwang , Jae-Young Park , In-Seak Hwang , Young-Wook Park
发明人： Jung-Hwan Oh , Ki-Hyun Hwang , Jae-Young Park , In-Seak Hwang , Young-Wook Park
IPC分类号： H01L27108
CPC分类号： H01L28/91 , H01L27/10855 , Y10T29/5111
摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

40. 发明授权

US06624069B2 Methods of forming integrated circuit capacitors having doped HSG electrodes 失效
标题翻译：形成具有掺杂HSG电极的集成电路电容器的方法
公开(公告)号：US06624069B2
公开(公告)日：2003-09-23
申请号：US09735244
申请日：2000-12-12
申请人： Seung-Hwan Lee , Sang-Hyeop Lee , Young-Sun Kim , Se-Jin Shim , You-Chan Jin , Ju-Tae Moon , Jin-Seok Choi , Young-Min Kim , Kyung-Hoon Kim , Kab-Jin Nam , Young-Wook Park , Seok-Jun Won , Young-Dae Kim
发明人： Seung-Hwan Lee , Sang-Hyeop Lee , Young-Sun Kim , Se-Jin Shim , You-Chan Jin , Ju-Tae Moon , Jin-Seok Choi , Young-Min Kim , Kyung-Hoon Kim , Kab-Jin Nam , Young-Wook Park , Seok-Jun Won , Young-Dae Kim
IPC分类号： H01L2144
CPC分类号： H01L28/84 , Y10S438/964
摘要： Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.
摘要翻译：形成集成电路电容器的方法包括以下步骤：通过在半导体衬底上形成导电层图案（例如，硅层）形成电容器的下电极，然后形成第一导电类型的半球形晶粒（HSG）硅表面层导电层图案。在导电层图案的外表面上包含HSG硅表面层增加给定横向尺寸的下电极的有效表面积。 HSG硅表面层还优选地充分掺杂有第一导电型掺杂剂（例如，N型），以使电容器反向偏置时可能在下电极中形成的任何耗尽层的尺寸最小化，从而提高电容器的特性 Cmin / Cmax比。扩散阻挡层（例如，氮化硅）也形成在下电极上，然后在扩散阻挡层上形成电介质层。扩散阻挡层优选由足够厚度的材料制成，以防止介电层和下电极之间的反应，并且还防止掺杂剂从HSG硅表面层向电介质层的扩散。电介质层还优选由具有高介电强度的材料形成以增加电容。

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