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31. 发明授权

US09356059B2 BSI image sensor chips and methods for forming the same 有权
标题翻译： BSI图像传感器芯片及其形成方法
公开(公告)号：US09356059B2
公开(公告)日：2016-05-31
申请号：US13352980
申请日：2012-01-18
申请人： Shiu-Ko JangJian , Kei-Wei Chen , Ying-Lang Wang
发明人： Shiu-Ko JangJian , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L29/04 , H01L27/146
CPC分类号： H01L27/14623 , H01L27/1464 , H01L27/14685
摘要： A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.
摘要翻译：一种器件包括具有正面和背面的半导体衬底。多晶硅层设置在半导体衬底的背面。多晶硅层包括掺杂有p型杂质的部分。电介质层设置在半导体衬底的背面，其中多晶硅层位于半导体衬底和多晶硅层之间。

32. 发明授权

US08890273B2 Methods and apparatus for an improved reflectivity optical grid for image sensors 有权
标题翻译：用于图像传感器的改进的反射率光栅的方法和装置
公开(公告)号：US08890273B2
公开(公告)日：2014-11-18
申请号：US13363280
申请日：2012-01-31
申请人： Shiu-Ko JangJian , Kei-Wei Chen , Ying-Lang Wang
发明人： Shiu-Ko JangJian , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L31/00 , H01L31/0224
CPC分类号： H01L31/022441 , H01L27/14623 , H01L27/14629 , H01L27/1464 , H01L31/022433
摘要： An improved reflectivity optical grid for image sensors. In an embodiment, a backside illuminated CIS device includes a semiconductor substrate having a pixel array area comprising a plurality of photosensors formed on a front side surface of the semiconductor substrate, each of the photosensors forming a pixel in the pixel array area; an optical grid material disposed over a backside surface of the semiconductor substrate, the optical grid material patterned to form an optical grid that bounds each of the pixels in the pixel array area and extending above the semiconductor substrate, the optical grid having sidewalls and a top portion; and a highly reflective coating formed over the optical grid, comprising a pure metal coating of a metal that is at least 99% pure, and a high-k dielectric coating over the pure metal coating that has a refractive index of greater than about 2.0. Methods are also disclosed.
摘要翻译：用于图像传感器的改进的反射光栅。在一个实施例中，背面照明的CIS器件包括具有像素阵列区域的半导体衬底，该像素阵列区域包括形成在半导体衬底的前侧表面上的多个光电传感器，每个光电传感器在像素阵列区域中形成像素; 设置在半导体衬底的背侧表面上的光栅格材料，所述光栅格材料被图案化以形成限定像素阵列区域中的每个像素并在半导体衬底上方延伸的光栅，所述光栅具有侧壁和顶部一部分; 以及形成在光栅上的高反射涂层，包括纯金属的纯金属涂层，其纯度至少为99％，纯金属涂层上的高k电介质涂层具有大于约2.0的折射率。还公开了方法。

33. 发明申请

US20130273686A1 Image Sensor Manufacturing Methods 有权
标题翻译：图像传感器制造方法
公开(公告)号：US20130273686A1
公开(公告)日：2013-10-17
申请号：US13445766
申请日：2012-04-12
申请人： Mu-Han Cheng , Kuo-Hsiu Wei , Kei-Wei Chen , Ying-Lang Wang
发明人： Mu-Han Cheng , Kuo-Hsiu Wei , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L31/0232 , H01L21/28
CPC分类号： H01L27/14623 , H01L27/1464 , H01L27/14687
摘要： Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.
摘要翻译：公开了半导体器件和背面照明（BSI）传感器制造方法。在一个实施例中，制造半导体器件的方法包括提供工件并在工件的前侧形成集成电路。使用镶嵌工艺在工件的背面上形成导电材料的格栅。

34. 发明授权

US08518819B2 Semiconductor device contact structures and methods for making the same 有权
标题翻译：半导体器件接触结构及其制造方法
公开(公告)号：US08518819B2
公开(公告)日：2013-08-27
申请号：US13049049
申请日：2011-03-16
申请人： Shih Chieh Chang , Chih-Chung Chang , Kei-Wei Chen , Ying-Lang Wang
发明人： Shih Chieh Chang , Chih-Chung Chang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53266 , H01L21/2855 , H01L21/76805 , H01L21/76814 , H01L21/76846 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.
摘要翻译：半导体接触结构和方法提供延伸穿过电介质材料并提供与包括硅化物材料和非硅化物材料（例如掺杂硅）的多个不同下层材料的接触的接触结构。接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。复合层可以由钛形成。在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。诸如钨或铜的导电插塞材料填充接触开口。

35. 发明申请

US20130153901A1 BSI Image Sensor Chips and Methods for Forming the Same 有权
标题翻译： BSI图像传感器芯片及其形成方法
公开(公告)号：US20130153901A1
公开(公告)日：2013-06-20
申请号：US13352980
申请日：2012-01-18
申请人： Shiu-Ko JangJian , Kei-Wei Chen , Ying-Lang Wang
发明人： Shiu-Ko JangJian , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L31/0368 , H01L21/20
CPC分类号： H01L27/14623 , H01L27/1464 , H01L27/14685
摘要： A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.
摘要翻译：一种器件包括具有正面和背面的半导体衬底。多晶硅层设置在半导体衬底的背面。多晶硅层包括掺杂有p型杂质的部分。介电层设置在半导体衬底的背面，其中多晶硅层位于半导体衬底和多晶硅层之间。

36. 发明授权

US08099861B2 Current-leveling electroplating/electropolishing electrode 有权
标题翻译：电流调平电镀/电解抛光电极
公开(公告)号：US08099861B2
公开(公告)日：2012-01-24
申请号：US12854214
申请日：2010-08-11
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
IPC分类号： B23P19/02 , B23P19/04 , B23P19/10 , B23P19/12 , C25D17/12 , C25D17/14 , C25D3/38
CPC分类号： H01L21/2885 , C25D17/001 , C25D17/12 , Y10T29/49208 , Y10T29/53204
摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
摘要翻译：公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。电流调平电极包括基极和由基极承载的至少一个子电极。所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

37. 发明申请

US20100314256A1 CURRENT-LEVELING ELECTROPLATING/ELECTROPOLISHING ELECTRODE 有权
标题翻译：电流电镀/电镀电极
公开(公告)号：US20100314256A1
公开(公告)日：2010-12-16
申请号：US12854214
申请日：2010-08-11
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
IPC分类号： C25D5/00 , H01R43/00 , C25F3/16 , C25F3/22
CPC分类号： H01L21/2885 , C25D17/001 , C25D17/12 , Y10T29/49208 , Y10T29/53204
摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
摘要翻译：公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。电流调平电极包括基极和由基极承载的至少一个子电极。所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

38. 发明申请

US20070205516A1 Low-k dielectric layer, semiconductor device, and method for fabricating the same 审中-公开
标题翻译：低k电介质层，半导体器件及其制造方法
公开(公告)号：US20070205516A1
公开(公告)日：2007-09-06
申请号：US11364088
申请日：2006-03-01
申请人： Kei-Wei Chen , Sheng-Wen Chen , Shiu-Ko Jangjian , Shih-Ho Lin , Hung-Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Sheng-Wen Chen , Shiu-Ko Jangjian , Shih-Ho Lin , Hung-Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53295 , H01L21/02126 , H01L21/022 , H01L21/0234 , H01L21/3121 , H01L21/3146 , H01L21/31633 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.
摘要翻译：低k电介质层，半导体器件及其制造方法。低k电介质层包括夹在两个低k电介质子层之间的硬化子层。硬化的子层通过利用氢等离子体或惰性气体等离子体轰击下面的低k电介质子层的方法形成。半导体器件包括覆盖衬底上的蚀刻停止层的低k电介质层，以及电连接到衬底的埋入电介质层和蚀刻停止层中的导电材料。

39. 发明授权

US06769959B2 Method and system for slurry usage reduction in chemical mechanical polishing 失效
标题翻译：化学机械抛光中浆料用量减少的方法和系统
公开(公告)号：US06769959B2
公开(公告)日：2004-08-03
申请号：US10050314
申请日：2002-01-15
申请人： Kei-Wei Chen , Ting-Chun Wang , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang , Ming-Wen Chen , Kuo-Hsiu Wei
发明人： Kei-Wei Chen , Ting-Chun Wang , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang , Ming-Wen Chen , Kuo-Hsiu Wei
IPC分类号： B24B100
CPC分类号： B24B37/04 , B24B57/02
摘要： A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.
摘要翻译：公开了一种利用其至少一个抛光垫在化学机械抛光操作中减少浆料使用的方法和系统。浆料可以间歇地供应到化学机械抛光装置。通常将浆料冲洗，使得所述浆料的一部分被捕获在与所述化学机械抛光装置相关联的至少一个抛光垫的多个孔中，其中仅使用最少量的所需浆料来进行所述化学机械抛光操作，从而减少浆料的使用并保持一致的浆料去除速率性能水平和其颗粒缺陷的减少。因此，本发明公开了一种用于以显着节省浆料使用的方式间歇地将浆料输送到化学机械抛光装置的方法和系统。

40. 发明授权

US09676114B2 Wafer edge trim blade with slots 有权
公开(公告)号：US09676114B2
公开(公告)日：2017-06-13
申请号：US13408327
申请日：2012-02-29
申请人： Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
发明人： Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
IPC分类号： B26D1/143 , B28D5/02 , B24D5/02 , B24D5/12 , B23D61/02 , B28D1/04 , B26D7/18 , B28D1/12
CPC分类号： B26D7/18 , B23D61/02 , B23D61/021 , B24D5/02 , B24D5/12 , B26D1/143 , B28D1/04 , B28D1/121 , B28D5/022 , Y10T83/0448 , Y10T83/9372
摘要： A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.

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