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    • 34. 发明申请
    • ESD protection for semiconductor products
    • 半导体产品的ESD保护
    • US20050148124A1
    • 2005-07-07
    • US11054189
    • 2005-02-09
    • Jun CaiAlvin SugermanSteven Park
    • Jun CaiAlvin SugermanSteven Park
    • H01L20060101H01L21/338H01L23/62H01L27/02H01L29/76H01L29/78
    • H01L29/7833H01L27/0266
    • A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gate is formed between the spaced apart surface isolation regions. Selected portions of the surface regions between the gate and the surface isolation regions are heterodoped to form p-n junctions having retrograde doping profiles beneath the substrate surface thereby lowering the breakdown voltage beneath the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions. Source and drain regions are formed in the substrate surface on opposite sides of the gate.
    • 用于形成具有用于承载击穿电流的ESD保护晶体管的垂直DMOS器件的工艺包括以下步骤:掩蔽第一极性类型的衬底并形成间隔开的表面隔离区域。 在间隔开的表面隔离区域之间形成绝缘栅极。 在栅极和表面隔离区域之间的表面区域的选定部分被杂散以形成在衬底表面下方具有逆向掺杂分布的pn结,从而降低异质部分之下的击穿电压,以将击穿电流的大部分引导到低于 衬底的表面并进入到异质区域之间的衬底的主体中。 源极和漏极区域形成在栅极的相对侧上的衬底表面中。
    • 35. 发明授权
    • ESD parasitic bipolar transistors with high resistivity regions in the collector
    • 集电极中具有高电阻率区域的ESD寄生双极晶体管
    • US06787880B2
    • 2004-09-07
    • US10437093
    • 2003-05-13
    • David HuJun Cai
    • David HuJun Cai
    • H01L218238
    • H01L27/027
    • A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.
    • 一种在寄生NPN的集电极内具有高电阻率区域的寄生双极硅化ESD器件的方法和结构。 该器件具有N-MOS晶体管和衬底接触的结构。 器件优选在掺杂区域上方具有硅化物区域。 本发明具有两种类型的高电阻率区域:1)隔离区域(例如,氧化物浅沟槽隔离(STI))和2)未掺杂或轻掺杂区域(例如沟道区)。 通道区域可以有栅极,栅极可以充电。 此外,可以在收集器下方形成任选的n - 阱(n-negative well)。 高电阻率区域增加了集电极电阻率,从而提高了寄生双极型ESD器件的性能。
    • 36. 发明授权
    • Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks
    • 低触发N MOS晶体管用于在没有硅化物块的完全硅化工艺下工作的ESD保护
    • US06444510B1
    • 2002-09-03
    • US09999246
    • 2001-12-03
    • David HuJun Cai
    • David HuJun Cai
    • H01L21336
    • H01L29/0847H01L27/0259H01L29/1087H01L29/66659H01L29/735H01L29/7835
    • An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n− well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region. The third n+ region is preferably shorted (or connected) to the first p+ region and the second n+ region. The third embodiment forms a second NPN parasitic bipolar using the third N+ region as an emitter. The forth embodiment contains the same elements as the third embodiment with the addition of a second gate over the first isolation region. The second gate is preferably connected to the third n+ region to the first p+ region and the second n+ region. The gate changes the electrical characteristics of the first parasitic bipolar transistor.
    • 使用硅化的寄生双极晶体管的ESD器件和方法。 第一实施例是由n + / n- / p- / n- / n +区组成的寄生双极结晶体管。 发射极由第二N +区和第二N-阱构成。 寄生基底由p-基底或阱形成。 集电极由第一阱和第一n +区形成。 第一实施例的好处是触发电压较低,因为n阱(发射极)与P-衬底(基极)之间的结以及P-衬底(基极)与n-阱之间的结有较低的交叉浓度 。 第二实施例与第一实施例类似,附加第一门。 第一栅极优选地连接到第一n +区域和Vpad。 第三实施例包含与第二实施例相同的元件,并添加第三n +区。 第三n +区域优选地与第一p +区域和第二n +区域短接(或连接)。 第三实施例使用第三N +区域作为发射器形成第二NPN寄生双极。 第四实施例包含与第三实施例相同的元件,在第一隔离区域上添加第二栅极。 第二栅极优选地连接到第三n +区到第一p +区和第二n +区。 门改变第一寄生双极晶体管的电特性。