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31. 发明申请

US20120081176A1 On-Die Voltage Regulation Using p-FET Header Devices with a Feedback Control Loop 失效
标题翻译：使用具有反馈控制回路的p-FET头部器件进行片上电压调节
公开(公告)号：US20120081176A1
公开(公告)日：2012-04-05
申请号：US13181848
申请日：2011-07-13
申请人： Thomas Buechner , Sebastian Ehrenreich , Tilman Gloekler , Bruno U. Spruth
发明人： Thomas Buechner , Sebastian Ehrenreich , Tilman Gloekler , Bruno U. Spruth
IPC分类号： H01L49/00 , H02J1/00
CPC分类号： G05F1/56
摘要： The invention relates to a voltage regulator circuit for providing voltage to an integrated circuit chip, comprising a reference voltage generator providing a reference voltage, a pFET header device having a plurality of pFET fingers, wherein each pFET finger in the plurality of pFET fingers is adapted for providing a different pFET output voltage to the integrated circuit chip, and a pFET control device for switching the plurality of pFET fingers depending on a comparison between the reference voltage and the pFET output voltage. The voltage regulator circuit allows for dynamically switching on or of the pFET fingers based on the output of the comparison of the reference voltage and the pFET output voltage, and thus allows for dynamically switching on or off, respectively, at least partly the integrated circuit chip.
摘要翻译：本发明涉及一种用于向集成电路芯片提供电压的电压调节器电路，包括提供参考电压的参考电压发生器，具有多个pFET指的pFET头部装置，其中多个pFET指状物中的每个pFET指状物适于用于向集成电路芯片提供不同的pFET输出电压，以及用于根据参考电压和pFET输出电压之间的比较来切换多个pFET指的pFET控制装置。电压调节器电路允许基于参考电压和pFET输出电压的比较的输出来动态地接通或引导pFET指，并且因此允许至少部分动态地接通或断开集成电路芯片。

32. 发明授权

US07564739B2 Storage cell design evaluation circuit including a wordline timing and cell access detection circuit 失效
标题翻译：存储单元设计评估电路，包括字线定时和单元访问检测电路
公开(公告)号：US07564739B2
公开(公告)日：2009-07-21
申请号：US12125011
申请日：2008-05-21
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Kai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Kai Ngo
IPC分类号： G11C8/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

33. 发明申请

US20080178129A1 Comparator Circuit and Method for Operating a Comparator Circuit 审中-公开
标题翻译：比较器电路和操作比较器电路的方法
公开(公告)号：US20080178129A1
公开(公告)日：2008-07-24
申请号：US11965186
申请日：2007-12-27
申请人： Sebastian Ehrenreich
发明人： Sebastian Ehrenreich
IPC分类号： G06F17/50
CPC分类号： H03K3/356113 , H03K3/35613
摘要： A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure is described. The design structure includes a comparator circuit for comparing a first voltage signal to a second voltage signal comprising a first comparator and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition.
摘要翻译：描述了在用于设计，制造或测试设计的机器可读介质中体现的设计结构，设计结构。该设计结构包括用于将第一电压信号与包括第一比较器和第二比较器的第二电压信号进行比较的比较器电路和用于根据选择条件选择一个比较器的选择单元。

34. 发明授权

US06937847B2 Integrated RF signal level detector usable for automatic power level control 失效
标题翻译：集成RF信号电平检测器，可用于自动功率电平控制
公开(公告)号：US06937847B2
公开(公告)日：2005-08-30
申请号：US10327162
申请日：2002-12-20
申请人： Sebastian Ehrenreich , Lutz Dathe , Karl-Heinz Sandig
发明人： Sebastian Ehrenreich , Lutz Dathe , Karl-Heinz Sandig
IPC分类号： H03G3/30 , H04B7/005 , H04B1/38
CPC分类号： H04W52/52 , H03G3/3036 , H03G3/3052
摘要： A radio frequency signal level is determined by generating an AC reference voltage from a DC reference voltage and determining an envelope of the AC reference voltage in an envelope detector having substantially the same composition as an envelope detector for determining the envelope of the radio frequency signal. The AC reference voltage substantially eliminates any DC offset and thus induces a high immunity against temperature and power supply variations. Moreover, using substantially the same RF signal path for the RF signal and the reference signal, signal distortions cause by the RF signal path are substantially compensated for.
摘要翻译：通过从DC参考电压生成AC参考电压并确定包络检测器中的与包络检测器基本相同的组合的AC参考电压的包络来确定射频信号的包络来确定射频信号电平。 AC参考电压基本上消除了任何DC偏移，因此引起了对温度和电源变化的高抗扰性。此外，对于RF信号和参考信号使用基本相同的RF信号路径，基本上补偿由RF信号路径引起的信号失真。

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