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31. 发明授权

US08674515B2 3D integrated circuits structure 有权
标题翻译： 3D集成电路结构
公开(公告)号：US08674515B2
公开(公告)日：2014-03-18
申请号：US13364002
申请日：2012-02-01
申请人： Mukta G. Farooq , Subramanian S. Iyer , Steven J. Koester , Huilong Zhu
发明人： Mukta G. Farooq , Subramanian S. Iyer , Steven J. Koester , Huilong Zhu
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/80895 , H01L2224/80896 , H01L2224/81894 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06541 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.
摘要翻译：通过金属填充的硅连接3D布置中的至少两个集成电路的结构，其通过其连接第一集成电路中的连接焊盘和第二集成电路中的连接焊盘。

32. 发明授权

US08587121B2 Backside dummy plugs for 3D integration 有权
标题翻译：用于3D集成的背面虚拟插头
公开(公告)号：US08587121B2
公开(公告)日：2013-11-19
申请号：US12730403
申请日：2010-03-24
申请人： Steven J. Koester , Fei Liu
发明人： Steven J. Koester , Fei Liu
IPC分类号： H01L23/40
CPC分类号： H01L24/05 , H01L21/7682 , H01L21/76898 , H01L23/3677 , H01L23/481 , H01L23/585 , H01L24/08 , H01L24/80 , H01L2224/02372 , H01L2224/0401 , H01L2224/05024 , H01L2224/05094 , H01L2224/05095 , H01L2224/0557 , H01L2224/08145 , H01L2224/80006 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01327 , H01L2924/12044 , H01L2924/1301 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor structure includes backside dummy plugs embedded in a substrate. The backside dummy plugs can be a conductive structure that enhances vertical thermal conductivity of the semiconductor structure and provides electrical decoupling of signals in through-substrate vias (TSVs) in the substrate. The backside dummy plug can include a cavity to accommodate volume changes in other components in the substrate, thereby alleviating mechanical stress in the substrate during thermal cycling and operation of the semiconductor chip. The backside dummy plug including the cavity can be composed of an insulator material or a conductive material. The inventive structures can be employed to form three-dimensional structures having vertical chip integration, in which inter-wafer thermal conductivity is enhanced, cross-talk between signals through TSVs is reduced, and/or mechanical stress to the TSVs is reduced.
摘要翻译：半导体结构包括嵌入基板中的背面虚拟插头。背面虚拟插头可以是导电结构，其增强了半导体结构的垂直导热性并且提供了在衬底中的贯穿衬底通孔（TSV）中的信号的电去耦合。背面虚拟插头可以包括空腔以适应衬底中的其他部件的体积变化，从而在半导体芯片的热循环和操作期间减轻衬底中的机械应力。包括空腔的背面虚拟插头可以由绝缘体材料或导电材料构成。本发明的结构可以用于形成具有垂直芯片集成的三维结构，其中晶片间热导率提高，通过TSV的信号之间的串扰减少，和/或对TSV的机械应力降低。

33. 发明授权

US08492869B2 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer 有权
标题翻译：具有在较高成本的有源电路层之前堆叠的低成本有源电路层的3D集成电路器件
公开(公告)号：US08492869B2
公开(公告)日：2013-07-23
申请号：US13571920
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/50
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L21/8221 , H01L25/0657 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2221/68377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0557 , H01L2224/131 , H01L2224/16 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/80001 , H01L2924/014 , H01L2224/83 , H01L2224/11
摘要： A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.
摘要翻译：提供了3D集成电路结构。 3D集成电路结构包括接口晶片，其包括第一布线层，包括有源电路的第一有源电路层和包括有源电路的晶片。第一有源电路层面向下接合到接口晶片，并且晶片正面朝下地接合到第一有源电路层。第一有源电路层比晶片成本低。

34. 发明授权

US08415772B2 Method to prevent surface decomposition of III-V compound semiconductors 有权
标题翻译：防止III-V化合物半导体表面分解的方法
公开(公告)号：US08415772B2
公开(公告)日：2013-04-09
申请号：US13570989
申请日：2012-08-09
申请人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
发明人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
IPC分类号： H01L23/58
CPC分类号： H01L21/28264 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.
摘要翻译：提供了防止III-V族化合物半导体的表面分解的方法。该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

35. 发明授权

US08399336B2 Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer 有权
标题翻译：用于制造具有在较高成本的有源电路层之前堆叠的较低成本有源电路层的3D集成电路器件的方法
公开(公告)号：US08399336B2
公开(公告)日：2013-03-19
申请号：US12194211
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L21/8221 , H01L25/0657 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2221/68377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0557 , H01L2224/131 , H01L2224/16 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/80001 , H01L2924/014 , H01L2224/83 , H01L2224/11
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。第一有源电路层晶片比另一个晶片低成本。还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

36. 发明授权

US08343838B2 Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor by implanting blocking impurity into the strained-layer 有权
标题翻译：通过将阻塞杂质注入到应变层中来减少应变层场效应晶体管中位错诱发的泄漏的方法
公开(公告)号：US08343838B2
公开(公告)日：2013-01-01
申请号：US12539235
申请日：2009-08-11
申请人： Steven J. Koester
发明人： Steven J. Koester
IPC分类号： H01L21/8258
CPC分类号： H01L29/78 , H01L21/26506 , H01L21/26513 , H01L29/1041 , H01L29/1054 , H01L29/51 , H01L29/517 , H01L29/518
摘要： A structure and method of fabricating a semiconductor field-effect transistor (MOSFET) such as a strained Si n-MOSFET where dislocation or crystal defects spanning from source to drain is partially occupied by heavy p-type dopants. Preferably, the strained-layer n-MOSFET includes a Si, SiGe or SiGeC multi-layer structure having, in the region between source and drain, impurity atoms that preferentially occupy the dislocation sites so as to prevent shorting of source and drain via dopant diffusion along the dislocation. Advantageously, devices formed as a result of the invention are immune to dislocation-related failures, and therefore are more robust to processing and material variations. The invention thus relaxes the requirement for reducing the threading dislocation density in SiGe buffers, since the devices will be operable despite the presence of a finite number of dislocations.
摘要翻译：制造诸如应变Si n-MOSFET的半导体场效应晶体管（MOSFET）的结构和方法，其中跨越源极到漏极的位错或晶体缺陷部分地被重的p型掺杂剂占据。优选地，应变层n-MOSFET包括在源极和漏极之间的区域中具有优先占据位错位置的杂质原子的Si，SiGe或SiGeC多层结构，以便防止源极和漏极通过掺杂剂扩散而短路沿错位。有利地，作为本发明的结果形成的装置不受位错相关的故障的影响，因此对于处理和材料变化更加鲁棒。因此，本发明放松了降低SiGe缓冲器中的穿透位错密度的要求，因为即使存在有限数量的位错，器件也将是可操作的。

37. 发明申请

US20120309153A1 METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS 失效
公开(公告)号：US20120309153A1
公开(公告)日：2012-12-06
申请号：US13570980
申请日：2012-08-09
申请人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
发明人： Joel P. de Souza , Keith E. Fogel , Edward W. Kiewra , Steven J. Koester , Christopher C. Parks , Devendra K. Sadana , Shahab Siddiqui
IPC分类号： H01L21/336
CPC分类号： H01L21/28264 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

38. 发明申请

US20120309127A1 METHOD FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER 有权
标题翻译：使用界面波形作为永久载体制作3D集成电路设备的方法
公开(公告)号：US20120309127A1
公开(公告)日：2012-12-06
申请号：US13572037
申请日：2012-08-10
申请人： Mukta G. FAROOQ , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. FAROOQ , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/60
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译：提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

39. 发明授权

US08258031B2 Fabrication of a vertical heterojunction tunnel-FET 有权
标题翻译：垂直异质结隧道FET的制造
公开(公告)号：US08258031B2
公开(公告)日：2012-09-04
申请号：US12815902
申请日：2010-06-15
申请人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
发明人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/165 , H01L29/7391
摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.
摘要翻译：示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

40. 发明申请

US20120193678A1 FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET 有权
标题翻译：垂直异步隧道式FET的制造
公开(公告)号：US20120193678A1
公开(公告)日：2012-08-02
申请号：US13430041
申请日：2012-03-26
申请人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
发明人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/165 , H01L29/7391
摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.
摘要翻译：示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

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