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    • 34. 发明申请
    • Semiconductor memory device having different synchronizing timings depending on the value of CAS latency
    • 具有取决于CAS延迟值的不同同步定时的半导体存储器件
    • US20050088906A1
    • 2005-04-28
    • US10899369
    • 2004-07-26
    • Min-soo Kim
    • Min-soo Kim
    • G11C11/407G11C7/08G11C7/22G11C8/18G11C11/40G11C11/4076
    • G11C7/08G11C11/4076
    • A semiconductor memory device including a clock buffer, a column selection line decoder, a control signal generation circuit, and a column selection line driver is provided. The clock buffer receives an external clock signal and information about a column address strobe (CAS) latency and generates either a first clock signal which synchronizes with rising edges of the external clock signal or a second clock signal which synchronizes with falling edges of the external clock signal depending on the type of CAS latency information. The column selection line decoder receives and decodes a column selection address and outputs a decoding address used to select either a column selection line signal synchronized with the first or second clock signal. The control signal generation circuit outputs control signals that synchronize with one of the first and second clock signals. The column selection line driver drives the column selection line signal in synchronization with one of the first and second clock signal in response to the decoding address and the control signals.
    • 提供了包括时钟缓冲器,列选择线解码器,控制信号生成电路和列选择线驱动器的半导体存储器件。 时钟缓冲器接收外部时钟信号和关于列地址选通(CAS)延迟的信息,并产生与外部时钟信号的上升沿同步的第一时钟信号或与外部时钟的下降沿同步的第二时钟信号 信号取决于CAS延迟信息的类型。 列选择线解码器接收并解码列选择地址,并输出用于选择与第一或第二时钟信号同步的列选择线信号的解码地址。 控制信号发生电路输出与第一和第二时钟信号之一同步的控制信号。 响应于解码地址和控制信号,列选择线驱动器与第一和第二时钟信号之一同步地驱动列选择线信号。