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31. 发明授权

US07060574B2 Buried channel type transistor having a trench gate and method of manufacturing the same 有权
公开(公告)号：US07060574B2
公开(公告)日：2006-06-13
申请号：US10839951
申请日：2004-05-05
申请人： Ji-Young Kim , Chang-Sub Lee
发明人： Ji-Young Kim , Chang-Sub Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/105 , H01L29/1083 , H01L29/6659 , H01L29/66621 , H01L29/7834
摘要： In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to a sidewall of the trench, respectively. A gate electrode filling the trench is formed. Source/drain regions are formed at portions of the substrate adjacent to the sidewall of the gate electrode. Stopper regions are formed at portions of the substrate beneath the source/drain regions and beneath the first and second threshold voltage control regions, respectively. The buried channel type transistor has a high breakdown voltage between the source/drain regions although a threshold voltage thereof is low.

32. 发明授权

US06960507B2 Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same 有权
标题翻译：垂直双通道绝缘体上硅晶体管及其制造方法
公开(公告)号：US06960507B2
公开(公告)日：2005-11-01
申请号：US10759239
申请日：2004-01-20
申请人： Ji-Young Kim , Jin-Jun Park
发明人： Ji-Young Kim , Jin-Jun Park
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76 , H01L21/8234 , H01L27/088 , H01L27/11 , H01L29/423 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66787 , H01L29/42384 , H01L29/78696
摘要： A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.
摘要翻译：垂直双通道绝缘体上硅（SOI）场效应晶体管（FET）包括与衬底上的一对平行浅沟槽隔离层接触的一对两个垂直半导体层，源极，漏极和漏极所述一对垂直半导体层中的每一个上的沟道区域与所述一对垂直半导体层中的对置区域对准，所述一对垂直半导体层中的两个沟道区上的栅极氧化物和栅电极，源极电极和漏电极，电连接所述一对垂直半导体层的各个区域。

33. 发明申请

US20050213384A1 Semiconductor device and method of forming the same 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20050213384A1
公开(公告)日：2005-09-29
申请号：US11135775
申请日：2005-05-23
申请人： Ji-Young Kim , Sang-Yong Kim
发明人： Ji-Young Kim , Sang-Yong Kim
IPC分类号： H01L29/78 , H01L21/8234 , H01L23/31 , G11C11/34
CPC分类号： H01L29/6656 , H01L21/823437 , H01L21/823468 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device protecting the ends of a gate line and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line. According to the method, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. A protecting pattern is formed to cover the ends of the gate line. The protecting pattern may be formed of silicon nitride or silicon oxide. Since the protecting pattern protects ends of a gate line, it is possible to prevent gate electrodes from being damaged by a cleaning solution such as SC1 in a subsequent process.
摘要翻译：公开了保护栅极线的端部的半导体器件及其形成方法。半导体器件包括半导体衬底，跨越半导体衬底的栅极线和覆盖栅极线的端部的保护图案。根据该方法，在半导体衬底上形成栅极线。形成间隔件以覆盖栅极线的侧壁。形成保护图案以覆盖栅极线的端部。保护图案可以由氮化硅或氧化硅形成。由于保护图案保护栅极线的端部，因此可以防止在随后的工艺中栅电极被诸如SC1的清洁溶液损坏。

34. 发明授权

US06903404B2 Semiconductor memory device and method for manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06903404B2
公开(公告)日：2005-06-07
申请号：US10426153
申请日：2003-04-29
申请人： Ji-Young Kim
发明人： Ji-Young Kim
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/331 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/73
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10808 , H01L27/10885 , H01L27/10888
摘要： A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a predetermined active region and having substantially the same height as the bit line structures, a semiconductor layer formed in the predetermined active region surrounded by the bit line structures and the isolation layer and having substantially the same height as the bit line structures and the isolation layer, a plurality of word line structures arranged in parallel on the bit line structures, the isolation layer, and the semiconductor layer, and comprising a plurality of word lines and an insulating material surrounding the word lines, and source and drain regions formed in the semiconductor layer on either side of the word line structures.
摘要翻译：半导体存储器件包括多个位线结构并行布置在半导体衬底上并且具有多个位线和围绕位线的绝缘材料，隔离层形成在位线结构之间的空间部分中以限定预定的有源区并且具有与位线结构基本相同的高度;形成在由位线结构和隔离层围绕的预定有源区中并且具有与位线结构和隔离层基本相同的高度的半导体层，在位线结构，隔离层和半导体层上平行布置的多个字线结构，并且包括多个字线和围绕字线的绝缘材料，以及形成在半导体中的源极和漏极区域在字线结构的任一侧的层。

35. 发明申请

US20050098850A1 Semiconductor device with self-aligned junction contact hole and method of fabricating the same 有权
标题翻译：具有自对准接合孔的半导体器件及其制造方法
公开(公告)号：US20050098850A1
公开(公告)日：2005-05-12
申请号：US11009913
申请日：2004-12-10
申请人： Ji-Young Kim , Je-Min Park
发明人： Ji-Young Kim , Je-Min Park
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/76 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/00
CPC分类号： H01L21/76897 , H01L21/76229 , H01L21/823481
摘要： A plurality of trenches for defining active regions are formed in a semiconductor substrate, using a plurality of trench masks. A gap fill insulating layer is formed on the resulting structure to fill a gap region bounded by the trench and the trench masks. Next, the trench mask and the gap fill insulating layer are patterned to form a trench mask pattern and a gap fill insulating pattern for defining a slit-type opening, extending across and exposes the active region. A gate pattern is formed in the slit-type opening and the trench mask pattern is removed to form a contact opening exposing the active region. Next, a contact plug is formed to fill the contact opening. Here, the contact opening is self-alignedly formed using an etch selectivity between the trench mask and the gap fill insulating layer. The resulting contact opening is a vacancy in a rectangular parallelepiped shape.
摘要翻译：使用多个沟槽掩模在半导体衬底中形成用于限定有源区的多个沟槽。在所得结构上形成间隙填充绝缘层，以填充由沟槽和沟槽掩模界定的间隙区域。接下来，将沟槽掩模和间隙填充绝缘层图案化以形成沟槽掩模图案和间隙填充绝缘图案，用于限定狭缝型开口，延伸跨过并暴露活性区域。在狭缝型开口中形成栅极图案，并且去除沟槽掩模图案以形成暴露有源区的接触开口。接下来，形成接触插塞以填充接触开口。这里，使用沟槽掩模和间隙填充绝缘层之间的蚀刻选择性，自对准地形成接触开口。所形成的接触开口是长方体形状的空位。

36. 发明申请

US20050079661A1 Recessed gate transistor structure and method of forming the same 有权
标题翻译：嵌入式晶体管结构及其形成方法
公开(公告)号：US20050079661A1
公开(公告)日：2005-04-14
申请号：US10963928
申请日：2004-10-12
申请人： Min-Hee Cho , Ji-Young Kim
发明人： Min-Hee Cho , Ji-Young Kim
IPC分类号： H01L21/336 , H01L21/00 , H01L21/84
CPC分类号： H01L29/66621 , H01L29/41758 , H01L29/4238 , H01L29/66659 , H01L29/7834
摘要： Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.
摘要翻译：嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准，也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。该方法和结构降低了门之间的电容。该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。第一和第二绝缘层形成在基板的整个表面上。在有源区域的一部分中形成凹部。在凹部内形成栅极绝缘层，然后在凹部内形成第一栅极导电层。第二栅极导电层形成在第二绝缘层和第一栅极导电层上。随后，形成源/漏区。

37. 发明授权

US06710726B2 Serializer-deserializer circuit having increased margins for setup and hold time 失效
标题翻译：串行器 - 解串器电路具有增加的设置和保持时间的边距
公开(公告)号：US06710726B2
公开(公告)日：2004-03-23
申请号：US10317327
申请日：2002-12-12
申请人： Ji-Young Kim , Jae-yup Lee
发明人： Ji-Young Kim , Jae-yup Lee
IPC分类号： H03M900
CPC分类号： H03M9/00
摘要： A serializer-deserializer circuit having increased margins for setup and hold time is provided. The serializer-deserializer circuit comprises a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). The data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal. The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes an output signal of the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal. Instead of using the first clock signal input with the data signal, the serializer-deserializer circuit uses a signal, which is generated by an oscillator and thus has a small amount of jitter, as an input clock to the PLL so that a reference clock signal without noise is generated to improve the operation of the serializer-deserializer circuit. In addition, the reference clock signal output from the PLL is locked to the data signal to increase margins for setup and hold time during the latch operation of the data signal.
摘要翻译：提供了一种具有增加的建立和保持时间余量的串行器 - 解串器电路。串行器 - 解串器电路包括数据偏移控制电路，锁存电路，串行转换器电路和锁相环（PLL）。数据偏移控制电路接收第一时钟信号和数据信号，延迟数据信号，并响应于参考时钟信号输出延迟的数据信号。锁存电路根据参考时钟信号锁存和输出延迟的数据信号。串行转换器电路响应于参考时钟信号接收和串行锁存电路的输出信号以输出串行数据。 PLL根据外部参考时钟信号产生参考时钟信号。串行器 - 解串器电路不是使用与数据信号一起输入的第一时钟信号，而是使用由振荡器产生的信号，因此具有少量的抖动作为PLL的输入时钟，使得参考时钟信号不产生噪声，从而改善了串串器 - 解串器电路的运行。此外，从PLL输出的参考时钟信号被锁定到数据信号，以在数据信号的锁存操作期间增加用于建立和保持时间的裕度。

38. 发明授权

US10681196B2 Method for providing human network management service in mobile terminal 有权
公开(公告)号：US10681196B2
公开(公告)日：2020-06-09
申请号：US12753414
申请日：2010-04-02
申请人： Hye-Soo Lee , Ji-Young Kim , Seong-Hoon Kang , Sun-Haeng Jo
发明人： Hye-Soo Lee , Ji-Young Kim , Seong-Hoon Kang , Sun-Haeng Jo
IPC分类号： G06F3/0481 , H04M1/2745 , G06Q30/02 , H04M1/725
摘要： Provided are a mobile terminal and method for providing a human network management service in the mobile terminal, the method including receiving human network data from a social network service site; checking and converting a schema of each received human network data into a predetermined schema; and updating human network data in the mobile terminal according to the converted schema.

39. 发明授权

US08884340B2 Semiconductor devices including dual gate electrode structures and related methods 有权
标题翻译：包括双栅电极结构和相关方法的半导体器件
公开(公告)号：US08884340B2
公开(公告)日：2014-11-11
申请号：US13298644
申请日：2011-11-17
申请人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
发明人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
IPC分类号： H01L21/336 , H01L29/772 , G11C11/404 , H01L27/108 , H01L29/66 , H01L29/78 , G11C11/408 , H01L29/417 , H01L29/423 , H01L21/8234
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.
摘要翻译：半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。此外，第一和第二栅电极可以是电隔离的。还讨论了相关设备，结构，操作方法和制造方法。

40. 发明授权

US08835910B2 Organic light emitting display apparatus 有权
标题翻译：有机发光显示装置
公开(公告)号：US08835910B2
公开(公告)日：2014-09-16
申请号：US13171184
申请日：2011-06-28
申请人： Ji-Young Kim , Mu-Hyun Kim , Jin-Goo Kang , Dong-Kyu Lee , Jae-Bok Kim
发明人： Ji-Young Kim , Mu-Hyun Kim , Jin-Goo Kang , Dong-Kyu Lee , Jae-Bok Kim
IPC分类号： H01L29/08 , H01L27/32
CPC分类号： H01L27/3258 , H01L27/3246
摘要： An organic light emitting display apparatus in which image quality can be improved. The organic light emitting display apparatus includes: a substrate; a first electrode disposed on the substrate; a pixel definition layer formed on the first electrode and having an opening portion through which a region of the first electrode is exposed; an intermediate layer connected to the first electrode through the opening portion and including an organic emission layer; a second electrode electrically connected to the intermediate layer; and an inorganic planarization pattern portion disposed between the substrate and the first electrode and formed to at least correspond to the opening portion.
摘要翻译：一种能够提高图像质量的有机发光显示装置。有机发光显示装置包括：基板; 设置在所述基板上的第一电极; 形成在第一电极上并具有开口部分的像素限定层，第一电极的区域通过该开口部分露出; 中间层，其通过所述开口部分连接到所述第一电极并且包括有机发射层; 电连接到所述中间层的第二电极; 以及设置在所述基板和所述第一电极之间并且至少形成为至少对应于所述开口部分的无机平坦化图案部分。

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