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31. 发明申请

US20070004158A1 TRANSISTOR HAVING A GERMANIUM IMPLANT REGION LOCATED THEREIN AND A METHOD OF MANUFACTURE THEREFOR 审中-公开
标题翻译：具有位于其中的德国植被区域的晶体管及其制造方法
公开(公告)号：US20070004158A1
公开(公告)日：2007-01-04
申请号：US11469687
申请日：2006-09-01
申请人： Kaiping Liu , Zhiqiang Wu , Majid Mansoorz
发明人： Kaiping Liu , Zhiqiang Wu , Majid Mansoorz
IPC分类号： H01L29/80 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/2807 , H01L21/28105 , H01L21/823828 , H01L29/4983
摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.
摘要翻译：本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

32. 发明授权

US07064039B2 Method to produce localized halo for MOS transistor 有权
标题翻译：用于产生MOS晶体管的局部晕的方法
公开(公告)号：US07064039B2
公开(公告)日：2006-06-20
申请号：US10785623
申请日：2004-02-24
申请人： Kaiping Liu
发明人： Kaiping Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1083 , H01L29/6656 , H01L29/66636
摘要： Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a gate structure over the semiconductor substrate, wherein a dopant material is implanted at an angle around the gate structure to form a halo structure in a source/drain region of the substrate and underlying a portion of the gate structure. A trench is formed in the source/drain region of the semiconductor substrate thereby removing at least a portion of the halo structure in the source/drain region. A silicon material layer is then formed in the trench using an epitaxial deposition.
摘要翻译：讨论了用于在半导体器件的衬底中形成局部晕圈结构和逆行轮廓的方法。该方法包括在半导体衬底上提供栅极结构，其中掺杂剂材料以围绕栅极结构的角度被注入，以在衬底的源极/漏极区域中形成卤素结构，并且位于栅极结构的一部分的下方。在半导体衬底的源极/漏极区域中形成沟槽，从而去除源极/漏极区域中的至少一部分卤素结构。然后使用外延沉积在沟槽中形成硅材料层。

33. 发明申请

US20060054934A1 Using oxynitride spacer to reduce parasitic capacitance in CMOS devices 有权
标题翻译：使用氮氧化物间隔物来减少CMOS器件中的寄生电容
公开(公告)号：US20060054934A1
公开(公告)日：2006-03-16
申请号：US10938179
申请日：2004-09-11
申请人： Yuanning Chen , Haowen Bu , Kaiping Liu
发明人： Yuanning Chen , Haowen Bu , Kaiping Liu
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L29/6656 , H01L21/823864 , H01L29/66598 , H01L29/7833
摘要： A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an oxynitride (SiOxNyCz) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate 100, forming a gate structure 108 over the substrate, depositing a first layer 104 atop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiOxNyCz) layer 250 atop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layer 112 atop the oxynitride layer, and depositing a nitride layer 114B atop the second layer.
摘要翻译：互补金属氧化物半导体（CMOS）器件具有衬底100，设置在衬底顶部的栅极结构108和沉积在栅极结构108的相对侧上的间隔物250，以控制衬底中的深源极漏极区S，D的形成。间隔物250由氧氮化物（SiO x N y O z C z z）形成，其中x和y不为零，但z可以为零或更大这种氧氮化物间隔物减少寄生电容，从而提高器件性能。制造互补金属氧化物半导体（CMOS）器件的一部分的方法包括提供衬底100，在衬底上形成栅极结构108，在栅极结构的相对侧上沉积衬底顶部的第一层104，以形成在衬底中的深源极漏极区域，在第一层的顶部上沉积氧氮化物（SiO x N x N z C z z）层250（其中x 并且y不为零但z可以为零或更大），在氧氮化物层的顶部沉积第二层112，以及在第二层顶上沉积氮化物层114B。

34. 发明申请

US20050212041A1 Novel process method of source drain spacer engineering to improve transistor capacitance 审中-公开
标题翻译：源极间隔工程的新型工艺方法，以提高晶体管电容
公开(公告)号：US20050212041A1
公开(公告)日：2005-09-29
申请号：US11127941
申请日：2005-05-11
申请人： Zhiqiang Wu , Jihong Chen , Kaiping Liu
发明人： Zhiqiang Wu , Jihong Chen , Kaiping Liu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/76
CPC分类号： H01L21/2652 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66598 , H01L29/7833
摘要： A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.
摘要翻译：提出了一种形成相关晶体管的方法，从而减轻了短沟道效应和结电容，从而促进了切换速度的提高。通过在衬底内形成的源区和漏区相对深地注入掺杂剂，在衬底内形成补偿区。补偿区域比源极和漏极区域稍微间隔开。该间隔影响电位轮廓并降低晶体管内的结电容。通过形成和选择性地调节与晶体管的栅极结构相邻的侧壁间隔来实现源极和漏极区域与补偿区域之间的不同距离。这些间隔物用作植入衬底中的掺杂剂以形成源区和漏区以及补偿区的引导。

35. 发明授权

US06794235B1 Method of manufacturing a semiconductor device having a localized halo implant 有权
标题翻译：制造具有局部晕圈植入物的半导体器件的方法
公开(公告)号：US06794235B1
公开(公告)日：2004-09-21
申请号：US10455088
申请日：2003-06-05
申请人： Kaiping Liu , Zhiqiang Wu
发明人： Kaiping Liu , Zhiqiang Wu
IPC分类号： H01L218238
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823807 , H01L29/66537 , H01L29/78
摘要： The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.
摘要翻译：本发明提供一种半导体器件200，其具有位于其中的局部晕轮植入物250，因此制造方法以及包括该半导体器件的集成电路。在一个实施例中，半导体器件200包括位于衬底210上的栅极244，衬底210具有位于其中的源极和漏极230。在相同的实施例中，位于源极和漏极230的每一个附近的是局部晕轮注入250，每个局部晕轮植入物250具有垂直注入区域260和倾斜注入区域265.此外，在垂直注入区域 260和角度注入区域265是峰值浓度的区域。

36. 发明授权

US06660605B1 Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss 有权
标题翻译：通过双扩散工艺制造最佳HDD的方法来优化晶体管驱动电流结电容，隧道电流和沟道掺杂剂损耗
公开(公告)号：US06660605B1
公开(公告)日：2003-12-09
申请号：US10292722
申请日：2002-11-12
申请人： Kaiping Liu
发明人： Kaiping Liu
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are discussed for forming a transistor comprising a source/drain region having both a graded HDD portion and a sharp HDD portion in a semiconductor substrate. The method comprises a dual diffusion process, wherein a gate structure is provided over the semiconductor substrate having an offset spacer associated therewith. A first dopant material is implanted around the gate structure in the source/drain area to form a grade-HDD region in the substrate that is aligned to the offset spacer. A sidewall spacer is formed around the gate structure and covers the offset spacer. A second dopant material is then implanted in the source/drain area to form a source/drain region in the substrate aligned to the sidewall spacer, and the device is thermally processed in a first anneal. The sidewall spacer and the offset spacer are removed from the gate structure. A third dopant material is implanted in the source/drain area to form a sharp HDD region aligned to the gate structure, and the device is flash annealed in a second anneal.
摘要翻译：讨论了用于形成包括在半导体衬底中具有梯度HDD部分和锋利HDD部分的源极/漏极区域的晶体管的方法。该方法包括双扩散过程，其中栅极结构设置在半导体衬底上，该半导体衬底具有与其相关联的偏移间隔物。在源极/漏极区域中的栅极结构周围注入第一掺杂剂材料，以在衬底中形成与偏移间隔物对准的等级HDD区域。侧壁间隔件形成在栅极结构周围并且覆盖偏移间隔物。然后将第二掺杂剂材料注入到源极/漏极区域中，以在与衬底对准的衬底中形成源极/漏极区域，并且器件在第一退火中热处理。侧壁间隔件和偏移间隔件从栅极结构移除。将第三掺杂剂材料注入到源极/漏极区域中以形成与栅极结构对准的尖锐的HDD区域，并且器件在第二退火中进行闪光退火。

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