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31. 发明申请

US20100262778A1 Empirically Based Dynamic Control of Transmission of Victim Cache Lateral Castouts 有权
标题翻译：基于经验的动态控制受害者缓存横向铸件传动
公开(公告)号：US20100262778A1
公开(公告)日：2010-10-14
申请号：US12421180
申请日：2009-04-09
申请人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/127 , G06F2212/6026
摘要： In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：响应于数据请求，选择从较低级别高速缓冲存储器进行丢弃的受害者高速缓存行，并且选择多个处理单元之一的目标下级高速缓存。确定所选择的目标下层高速缓存是否为第一较低级别高速缓存的横向转移（LCO）命令提供了超过阈值数量的重试响应，如果是，则选择不同的目标低级高速缓存。此后，第一处理单元在互连结构上发出LCO命令。 LCO命令标识要丢弃的受害者缓存行，并指示目标下级缓存是受害缓存行的预期目标。响应于对LCO命令的成功的一致性响应，从第一低级缓存中移除受害者高速缓存行并保存在第二较低级缓存中。

32. 发明申请

US20100257317A1 Virtual Barrier Synchronization Cache 失效
标题翻译：虚拟障碍同步缓存
公开(公告)号：US20100257317A1
公开(公告)日：2010-10-07
申请号：US12419364
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问系统内存的虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括从系统存储器的虚拟屏障同步区域缓存VBSR行的缓存阵列和高速缓存控制器。高速缓存控制器响应于来自处理器核心的存储请求来更新特定VBSR线路，通过发送来同时保存特定VBSR线路的副本的多个处理单元中的彼此之间的高速缓存阵列的非阻塞更新互连结构上的VBSR更新命令。

33. 发明申请

US20100235577A1 VICTIM CACHE LATERAL CASTOUT TARGETING 失效
公开(公告)号：US20100235577A1
公开(公告)日：2010-09-16
申请号：US12340511
申请日：2008-12-19
申请人： Guy L. Guthrie , Michael S. Siegel , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Michael S. Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0862
摘要： A data processing system includes a plurality of processing units coupled by an interconnect fabric. In response to a data request, a victim cache line is selected for castout from a first lower level cache of a first processing unit, and a target lower level cache of one of the plurality of processing units is selected based upon architectural proximity of the target lower level cache to a home system memory to which the address of the victim cache line is assigned. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：数据处理系统包括通过互连结构耦合的多个处理单元。响应于数据请求，从第一处理单元的第一较低级别高速缓存中选择牺牲缓存行来进行舍弃，并且基于目标的体系结构接近来选择多个处理单元之一的目标下级高速缓存低级缓存到分配了受害者缓存行的地址的归属系统存储器。所述第一处理单元在所述互连结构上发出侧向锁定（LCO）命令，所述侧向锁定（LCO）命令标识要从所述第一低级缓存中抛出的所述牺牲缓存线，并且指示所述目标低级缓存是预期目的地。响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

34. 发明申请

US20100100682A1 Victim Cache Replacement 有权
标题翻译：受害者缓存替换
公开(公告)号：US20100100682A1
公开(公告)日：2010-04-22
申请号：US12256002
申请日：2008-10-22
申请人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.
摘要翻译：数据处理系统包括具有相关联的高级缓存和较低级别的受害缓存的处理器核心。响应于指定对目标一致性粒子的不修改访问的处理器核心的存储器访问请求，确定存储器访问请求是否在较低级别的受害缓存的目录中命中或丢失。响应于确定存储器访问请求在数据有效的相干状态中击中较低级别的受害者高速缓存，则较低级别的受害者缓存将存储器访问请求的目标一致性颗粒提供给高级缓存。如果存储器访问请求是第一类型，则较低级别的受害者缓存在共享相干状态下保留较低级别的受害者缓存中的目标一致性粒子，如果存储器访问请求是第二类型，则使目标一致性粒子无效。

35. 发明授权

US07689891B2 Method and system for handling stuck bits in cache directories 有权
标题翻译：用于处理缓存目录中的卡位的方法和系统
公开(公告)号：US07689891B2
公开(公告)日：2010-03-30
申请号：US11225640
申请日：2005-09-13
申请人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke
发明人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory which detects an error in a stored tag having an address field, a state field and an error-correction field, determines that the error is associated with a stuck bit of the directory member, marks the directory member as defective, and casts out corrected address information. The error is detected during processing of a cache directory access request, and is determined to be associated with a stuck bit of the directory member by attempting to correct a first error and then detecting a second error after the first correction attempt. The address information is cast out by routing a surrogate tag contained in a surrogate member of the cache directory through error-correction pipeline circuitry while transmitting the address information from the surrogate member to a cast-out machine.
摘要翻译：一种处理高速缓冲存储器的目录中的卡住位的方法，该高速缓冲存储器的目录中检测到具有地址字段，状态字段和纠错字段的存储标签中的错误，确定该错误与该目录的卡住位相关联会员，将目录成员标记为有缺陷，并丢弃修正的地址信息。在处理高速缓存目录访问请求期间检测到错误，并且通过尝试校正第一错误然后在第一次校正尝试之后检测第二错误来确定与目录成员的卡住位相关联。通过错误校正流水线电路路由包含在高速缓存目录的代理成员中的代理标签，同时将地址信息从代理成员发送到投放机器，来丢弃地址信息。

36. 发明申请

US20090198933A1 Method and Apparatus for Handling Multiple Memory Requests Within a Multiprocessor System 有权
标题翻译：在多处理器系统中处理多个存储器请求的方法和装置
公开(公告)号：US20090198933A1
公开(公告)日：2009-08-06
申请号：US12024181
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/14
CPC分类号： G06F9/526
摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.
摘要翻译：公开了一种在多处理器系统内处理多个存储器请求的方法。锁控制部分最初被分配给系统存储器内的数据块。响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。

37. 发明授权

US07536513B2 Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state 有权
标题翻译：数据处理系统，缓存系统和方法，用于基于标记的高速缓存状态在不引用低级缓存的情况下在互连结构上发出请求
公开(公告)号：US07536513B2
公开(公告)日：2009-05-19
申请号：US11095734
申请日：2005-03-31
申请人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831
摘要： In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.
摘要翻译：响应于主机接收到指示目标地址的存储器访问请求，主机访问高速缓存层级的高级缓存的第一高速缓存目录。响应于目标地址与具有有效地址标签的条目和第一无效一致性状态在第一高速缓存目录中相关联的目标地址，主机在不考虑与该互连结构相关联的一致性状态的情况下发布指定互连结构上的目标地址的请求目标地址在缓存层次结构的较低级缓存的第二高速缓存目录中。响应于相对于第一高速缓存目录具有第二无效一致性状态的目标地址，主机在确定与第二高速缓存目录中的目标地址相关联的一致性状态之后，在互连结构上发出指定目标地址的请求缓存层次结构的较低级缓存。

38. 发明授权

US07533321B2 Fault tolerant encoding of directory states for stuck bits 有权
标题翻译：卡位的目录状态的容错编码
公开(公告)号：US07533321B2
公开(公告)日：2009-05-12
申请号：US11225570
申请日：2005-09-13
申请人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke
发明人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke
IPC分类号： G11C29/00
CPC分类号： G11C29/832 , G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.
摘要翻译：一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员的目录成员中的卡住位。多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码。还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。

39. 发明授权

US07512742B2 Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效
标题翻译：数据处理系统，缓存系统和精确形成指示广播范围的无效一致性状态的方法
公开(公告)号：US07512742B2
公开(公告)日：2009-03-31
申请号：US11333615
申请日：2006-01-17
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。如果分配了与存储器块相关联的地址的归属系统存储器在第一相关域内，则确定。如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成一致性状态下，内存块被缓存在第一个相干域之外。

40. 发明授权

US07484042B2 Data processing system and method for predictively selecting a scope of a prefetch operation 失效
标题翻译：用于预测性地选择预取操作的范围的数据处理系统和方法
公开(公告)号：US07484042B2
公开(公告)日：2009-01-27
申请号：US11465587
申请日：2006-08-18
申请人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0862
摘要： A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, and a cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents of the data array, and a cache controller including a prefetch predictor. The prefetch predictor determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address. The cache controller issues the first prefetch operation on the interconnect fabric with the predicted scope.
摘要翻译：数据处理系统至少包括第一和第二相关域，每个域包含至少一个处理单元，耦合第一和第二相干域的互连结构以及第一相干域内的高速缓冲存储器。高速缓冲存储器包括数据阵列，数据阵列的内容的高速缓存目录以及包括预取预测器的高速缓存控制器。预取预测器基于具有不同的第二目标地址的先前的第二预取操作的范围来确定具有第一目标地址的第一预取操作的互连结构上的广播的预测范围。高速缓存控制器以预测的范围在互连结构上发出第一个预取操作。

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